Implemented REG_TO_MEM GPU opcode
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@ -517,6 +517,9 @@ bool CommandProcessor::ExecutePacketType3(RingbufferReader* reader,
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case PM4_REG_RMW:
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result = ExecutePacketType3_REG_RMW(reader, packet, count);
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break;
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case PM4_REG_TO_MEM:
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result = ExecutePacketType3_REG_TO_MEM(reader, packet, count);
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break;
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case PM4_COND_WRITE:
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result = ExecutePacketType3_COND_WRITE(reader, packet, count);
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break;
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@ -586,7 +589,14 @@ bool CommandProcessor::ExecutePacketType3(RingbufferReader* reader,
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reader->Skip(count);
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break;
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case 0x00:
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// Not a valid opcode. Something's up.
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XELOGGPU("Invalid GPU Opcode Detected 0x%x", 0x00);
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assert_always();
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break;
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default:
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XELOGGPU("Not Implemented GPU OPCODE: 0x%X\t\tCOUNT: %d\n", opcode, count);
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reader->Skip(count);
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break;
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}
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@ -781,6 +791,29 @@ bool CommandProcessor::ExecutePacketType3_REG_RMW(RingbufferReader* reader,
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return true;
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}
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bool CommandProcessor::ExecutePacketType3_REG_TO_MEM(RingbufferReader* reader,
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uint32_t packet,
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uint32_t count) {
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// Copy Register to Memory (?)
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// Count is 2, assuming a Register Addr and a Memory Addr.
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uint32_t reg_addr = reader->Read();
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uint32_t mem_addr = reader->Read();
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uint32_t reg_val;
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assert_true(reg_addr < RegisterFile::kRegisterCount);
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reg_val = register_file_->values[reg_addr].u32;
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auto endianness = static_cast<Endian>(mem_addr & 0x3);
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mem_addr &= ~0x3;
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reg_val = GpuSwap(reg_val, endianness);
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xe::store(memory_->TranslatePhysical(mem_addr), reg_val);
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trace_writer_.WriteMemoryWrite(CpuToGpu(mem_addr), 4);
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return true;
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}
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bool CommandProcessor::ExecutePacketType3_COND_WRITE(RingbufferReader* reader,
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uint32_t packet,
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uint32_t count) {
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@ -136,6 +136,8 @@ class CommandProcessor {
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uint32_t packet, uint32_t count);
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bool ExecutePacketType3_REG_RMW(RingbufferReader* reader, uint32_t packet,
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uint32_t count);
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bool ExecutePacketType3_REG_TO_MEM(RingbufferReader* reader, uint32_t packet,
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uint32_t count);
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bool ExecutePacketType3_COND_WRITE(RingbufferReader* reader, uint32_t packet,
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uint32_t count);
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bool ExecutePacketType3_EVENT_WRITE(RingbufferReader* reader, uint32_t packet,
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