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[GPU] Complete some register bitfield declarations

This commit is contained in:
Triang3l 2020-12-12 20:01:41 +03:00
parent e348d6361e
commit b106aa88e6
2 changed files with 11 additions and 12 deletions
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4
src/xenia/gpu/registers.h
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@ -260,9 +260,9 @@ union PA_SU_SC_MODE_CNTL {
uint32_t multi_prim_ib_ena : 1; // +21
uint32_t : 1; // +22
uint32_t quad_order_enable : 1; // +23
uint32_t sc_one_quad_per_clock : 1; // +24
// WAIT_RB_IDLE_ALL_TRI and WAIT_RB_IDLE_FIRST_TRI_NEW_STATE were added on
// Adreno.
// TODO(Triang3l): Find SC_ONE_QUAD_PER_CLOCK offset.
};
uint32_t value;
static constexpr Register register_index = XE_GPU_REG_PA_SU_SC_MODE_CNTL;
@ -298,7 +298,7 @@ union PA_SC_VIZ_QUERY {
// discard geometry after test (but use for testing)
uint32_t kill_pix_post_hi_z : 1; // +7
// not used with d3d
uint32_t kill_pix_detail_mask : 1; // +8
uint32_t kill_pix_post_detail_mask : 1; // +8
};
uint32_t value;
static constexpr Register register_index = XE_GPU_REG_PA_SC_VIZ_QUERY;

3
src/xenia/gpu/xenos.h
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@ -1039,8 +1039,7 @@ XEPACKEDUNION(xe_gpu_texture_fetch_t, {
ClampMode clamp_y : 3; // +13
ClampMode clamp_z : 3; // +16
SignedRepeatingFractionMode signed_rf_mode_all : 1; // +19
// TODO(Triang3l): 1 or 2 dim_tbd bits?
uint32_t unk_0 : 2; // +20
uint32_t dim_tbd : 2; // +20
uint32_t pitch : 9; // +22 byte_pitch >> 5
uint32_t tiled : 1; // +31