[Vulkan] Fix another incorrect pipeline stage barrier

2017-12-21 15:13:01 -06:00 · 2017-12-21 15:13:01 -06:00 · ab7dce53ec
parent 697eccf23e
commit ab7dce53ec
1 changed files with 1 additions and 1 deletions
--- a/src/xenia/gpu/vulkan/buffer_cache.cc
+++ b/src/xenia/gpu/vulkan/buffer_cache.cc
@ -320,7 +320,7 @@ std::pair<VkBuffer, VkDeviceSize> BufferCache::UploadIndexBuffer(
      source_length,
  };
  vkCmdPipelineBarrier(command_buffer, VK_PIPELINE_STAGE_HOST_BIT,
-                       VK_PIPELINE_STAGE_TOP_OF_PIPE_BIT, 0, 0, nullptr, 1,
+                       VK_PIPELINE_STAGE_VERTEX_INPUT_BIT, 0, 0, nullptr, 1,
                       &barrier, 0, nullptr);

  CacheTransientData(source_addr, source_length, offset);