Merge pull request #718 from parkerlamb/disasm_fixes
PPC disassembly fixes
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commit
a2fb0a06fe
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@ -86,6 +86,7 @@ struct PPCDecodeData {
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union {
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union {
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uint32_t value_;
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uint32_t value_;
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struct {
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struct {
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uint32_t : 2;
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uint32_t DS : 14;
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uint32_t DS : 14;
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uint32_t RA : 5;
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uint32_t RA : 5;
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uint32_t RT : 5;
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uint32_t RT : 5;
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@ -1689,9 +1689,9 @@ void PrintDisasm_mtmsrd(const PPCDecodeData& d, StringBuffer* str) {
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str->AppendFormat("r%d", d.X.RS());
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str->AppendFormat("r%d", d.X.RS());
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}
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}
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void PrintDisasm_mtspr(const PPCDecodeData& d, StringBuffer* str) {
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void PrintDisasm_mtspr(const PPCDecodeData& d, StringBuffer* str) {
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// mtmspr [SPR], [RS]
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// mtspr [SPR], [RS]
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size_t str_start = str->length();
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size_t str_start = str->length();
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str->Append("mtmspr");
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str->Append("mtspr");
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PadStringBuffer(str, str_start, kNamePad);
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PadStringBuffer(str, str_start, kNamePad);
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str->AppendFormat("%d", d.XFX.SPR());
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str->AppendFormat("%d", d.XFX.SPR());
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str->Append(", ");
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str->Append(", ");
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@ -908,7 +908,7 @@
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<insn mnem="mtspr" opcode="7c0003a6" form="XFX" group="c" desc="Move to Special-Purpose Register">
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<insn mnem="mtspr" opcode="7c0003a6" form="XFX" group="c" desc="Move to Special-Purpose Register">
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<in field="RS" />
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<in field="RS" />
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<out field="SPR" />
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<out field="SPR" />
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<disasm>mtmspr [SPR], [RS]</disasm>
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<disasm>mtspr [SPR], [RS]</disasm>
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</insn>
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</insn>
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<insn mnem="mulhdx" opcode="7c000092" form="XO" group="i" desc="Multiply High Doubleword">
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<insn mnem="mulhdx" opcode="7c000092" form="XO" group="i" desc="Multiply High Doubleword">
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<in field="RA" />
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<in field="RA" />
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@ -137,6 +137,7 @@ def generate_opcodes(insns):
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w0('#define XENIA_CPU_PPC_PPC_OPCODE_H_')
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w0('#define XENIA_CPU_PPC_PPC_OPCODE_H_')
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w0('')
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w0('')
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w0('#include <cstdint>')
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w0('#include <cstdint>')
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w0('#include <cstdlib>')
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w0('')
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w0('')
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w0('namespace xe {')
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w0('namespace xe {')
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w0('namespace cpu {')
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w0('namespace cpu {')
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@ -176,6 +177,7 @@ def generate_table(insns):
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w0('// This code was autogenerated by %s. Do not modify!' % (sys.argv[0]))
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w0('// This code was autogenerated by %s. Do not modify!' % (sys.argv[0]))
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w0('// clang-format off')
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w0('// clang-format off')
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w0('#include <cstdint>')
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w0('#include <cstdint>')
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w0('#include <cstdlib>')
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w0('')
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w0('')
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w0('#include "xenia/base/assert.h"')
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w0('#include "xenia/base/assert.h"')
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w0('#include "xenia/cpu/ppc/ppc_opcode.h"')
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w0('#include "xenia/cpu/ppc/ppc_opcode.h"')
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@ -279,6 +281,7 @@ def generate_disasm(insns):
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w0('// This code was autogenerated by %s. Do not modify!' % (sys.argv[0]))
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w0('// This code was autogenerated by %s. Do not modify!' % (sys.argv[0]))
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w0('// clang-format off')
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w0('// clang-format off')
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w0('#include <cstdint>')
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w0('#include <cstdint>')
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w0('#include <cstdlib>')
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w0('')
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w0('')
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w0('#include "xenia/base/assert.h"')
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w0('#include "xenia/base/assert.h"')
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w0('#include "xenia/cpu/ppc/ppc_decode_data.h"')
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w0('#include "xenia/cpu/ppc/ppc_decode_data.h"')
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@ -410,6 +413,7 @@ def generate_lookup(insns):
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w0('// This code was autogenerated by %s. Do not modify!' % (sys.argv[0]))
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w0('// This code was autogenerated by %s. Do not modify!' % (sys.argv[0]))
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w0('// clang-format off')
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w0('// clang-format off')
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w0('#include <cstdint>')
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w0('#include <cstdint>')
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w0('#include <cstdlib>')
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w0('')
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w0('')
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w0('#include "xenia/base/assert.h"')
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w0('#include "xenia/base/assert.h"')
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w0('#include "xenia/cpu/ppc/ppc_opcode.h"')
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w0('#include "xenia/cpu/ppc/ppc_opcode.h"')
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