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vsel tests.

This commit is contained in:
Ben Vanik 2015-01-11 21:32:34 -08:00
parent e48d9a44c7
commit 9a66629725
5 changed files with 51 additions and 0 deletions
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2
src/alloy/frontend/ppc/ppc_emit_altivec.cc
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@ -1344,6 +1344,8 @@ XEEMITTER(vrsqrtefp128, VX128_3(6, 1648), VX128_3)(PPCHIRBuilder& f,
int InstrEmit_vsel_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb, int InstrEmit_vsel_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb,
uint32_t vc) { uint32_t vc) {
// For each bit:
// VRTi <- ((VRC)i=0) ? (VRA)i : (VRB)i
Value* v = f.Select(f.LoadVR(vc), f.LoadVR(va), f.LoadVR(vb)); Value* v = f.Select(f.LoadVR(vc), f.LoadVR(va), f.LoadVR(vb));
f.StoreVR(vd, v); f.StoreVR(vd, v);
return 0; return 0;

BIN
src/alloy/frontend/ppc/test/bin/instr_vsel.bin Normal file
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17
src/alloy/frontend/ppc/test/bin/instr_vsel.dis Normal file
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@ -0,0 +1,17 @@
/vagrant/src/alloy/frontend/ppc/test/bin//instr_vsel.o: file format elf64-powerpc
Disassembly of section .text:
0000000000100000 <test_vsel_1>:
100000: 10 a3 21 6a vsel v5,v3,v4,v5
100004: 4e 80 00 20 blr
0000000000100008 <test_vsel_2>:
100008: 10 a3 21 6a vsel v5,v3,v4,v5
10000c: 4e 80 00 20 blr
0000000000100010 <test_vsel_3>:
100010: 10 a3 21 6a vsel v5,v3,v4,v5
100014: 4e 80 00 20 blr

3
src/alloy/frontend/ppc/test/bin/instr_vsel.map Normal file
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@ -0,0 +1,3 @@
0000000000000000 t test_vsel_1
0000000000000008 t test_vsel_2
0000000000000010 t test_vsel_3

29
src/alloy/frontend/ppc/test/instr_vsel.s Normal file
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@ -0,0 +1,29 @@
test_vsel_1:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v5 [00000000, 00000000, 00000000, 00000000]
vsel v5, v3, v4, v5
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_vsel_2:
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v5 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsel v5, v3, v4, v5
blr
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [10111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [10111213, 14151617, 18191A1B, 1C1D1E1F]
test_vsel_3:
#_ REGISTER_IN v3 [0C010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_IN v4 [1D111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_IN v5 [10101010, 10101010, 10101010, 10101010]
vsel v5, v3, v4, v5
blr
#_ REGISTER_OUT v3 [0C010203, 04050607, 08090A0B, 0C0D0E0F]
#_ REGISTER_OUT v4 [1D111213, 14151617, 18191A1B, 1C1D1E1F]
#_ REGISTER_OUT v5 [1C111213, 14151617, 18191A1B, 1C1D1E1F]