add writeback base/size and xps base/size registers, EVENT_WRITE_SHD check
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@ -897,7 +897,17 @@ bool COMMAND_PROCESSOR::ExecutePacketType3_EVENT_WRITE_SHD(
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auto endianness = static_cast<xenos::Endian>(address & 0x3);
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address &= ~0x3;
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data_value = GpuSwap(data_value, endianness);
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xe::store(memory_->TranslatePhysical(address), data_value);
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uint8_t* write_destination = memory_->TranslatePhysical(address);
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if (address > 0x1FFFFFFF) {
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uint32_t writeback_base = register_file_->values[XE_GPU_REG_WRITEBACK_BASE].u32;
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uint32_t writeback_size = register_file_->values[XE_GPU_REG_WRITEBACK_SIZE].u32;
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uint32_t writeback_offset = address - writeback_base;
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//check whether the guest has written writeback base. if they haven't, skip the offset check
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if (writeback_base != 0 && writeback_offset < writeback_size) {
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write_destination = memory_->TranslateVirtual(0x7F000000 + writeback_offset);
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}
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}
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xe::store(write_destination, data_value);
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trace_writer_.WriteMemoryWrite(CpuToGpu(address), 4);
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return true;
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}
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@ -72,10 +72,14 @@ XE_GPU_REGISTER(0x0855, kDword, MC1_PERFCOUNTER0_SELECT)
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XE_GPU_REGISTER(0x0856, kDword, MC1_PERFCOUNTER0_HI)
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XE_GPU_REGISTER(0x0857, kDword, MC1_PERFCOUNTER0_LOW)
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XE_GPU_REGISTER(0x0A02, kDword, UNKNOWN_0A02)
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XE_GPU_REGISTER(0x0A03, kDword, UNKNOWN_0A03)
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XE_GPU_REGISTER(0x0A04, kDword, UNKNOWN_0A04)
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XE_GPU_REGISTER(0x0A05, kDword, UNKNOWN_0A05)
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//base GPU virtual address of the xps region. Most guests write 0xC0100000 here
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XE_GPU_REGISTER(0x0A02, kDword, XPS_BASE)
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//will usually be set higher, but is effectively 0x700000 bytes long
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XE_GPU_REGISTER(0x0A03, kDword, XPS_SIZE)
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//usually 0xC0000000
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XE_GPU_REGISTER(0x0A04, kDword, WRITEBACK_BASE)
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//usually 0x0100000
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XE_GPU_REGISTER(0x0A05, kDword, WRITEBACK_SIZE)
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XE_GPU_REGISTER(0x0A18, kDword, MH_PERFCOUNTER0_SELECT)
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XE_GPU_REGISTER(0x0A19, kDword, MH_PERFCOUNTER0_HI)
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