Revert "[D3D12] Re-add accidentally deleted RT update trigger and treat Z test and write bits separately"
This reverts commit 25cc189e99
.
This commit is contained in:
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25cc189e99
commit
8f51855c8f
src/xenia/gpu/d3d12
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@ -1199,7 +1199,8 @@ bool D3D12CommandProcessor::IssueDraw(PrimitiveType primitive_type,
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uint32_t color_mask = GetCurrentColorMask(pixel_shader);
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uint32_t rb_depthcontrol = regs[XE_GPU_REG_RB_DEPTHCONTROL].u32;
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uint32_t rb_stencilrefmask = regs[XE_GPU_REG_RB_STENCILREFMASK].u32;
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if (!memexport_used && !color_mask && !(rb_depthcontrol & 0x4) &&
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if (!memexport_used && !color_mask &&
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((rb_depthcontrol & (0x2 | 0x4)) != (0x2 | 0x4)) &&
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(!(rb_depthcontrol & 0x1) || !(rb_stencilrefmask & (0xFF << 16)))) {
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// Not writing to color, depth or stencil, so doesn't draw.
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return true;
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@ -2017,12 +2018,12 @@ void D3D12CommandProcessor::UpdateSystemConstantValues(
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// Disable depth and stencil if it aliases a color render target (for
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// instance, during the XBLA logo in Banjo-Kazooie, though depth writing is
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// already disabled there).
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if (IsROVUsedForEDRAM() && (rb_depthcontrol & (0x1 | 0x2 | 0x4))) {
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if (IsROVUsedForEDRAM() && (rb_depthcontrol & (0x1 | 0x2))) {
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uint32_t edram_base_depth = rb_depth_info & 0xFFF;
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for (uint32_t i = 0; i < 4; ++i) {
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if ((color_mask & (0xF << (i * 4))) &&
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edram_base_depth == (color_infos[i] & 0xFFF)) {
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rb_depthcontrol &= ~(uint32_t(0x1 | 0x2 | 0x4));
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rb_depthcontrol &= ~(uint32_t(0x1 | 0x2));
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break;
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}
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}
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@ -2099,30 +2100,30 @@ void D3D12CommandProcessor::UpdateSystemConstantValues(
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uint32_t(ColorRenderTargetFormat::k_8_8_8_8_GAMMA)) {
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flags |= DxbcShaderTranslator::kSysFlag_Color3Gamma;
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}
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if (IsROVUsedForEDRAM()) {
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uint32_t depth_comparison;
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if (rb_depthcontrol & 0x2) {
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depth_comparison = (rb_depthcontrol >> 4) & 0x7;
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} else {
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depth_comparison = 0b111;
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if (IsROVUsedForEDRAM() && (rb_depthcontrol & (0x1 | 0x2))) {
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flags |= DxbcShaderTranslator::kSysFlag_DepthStencil;
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if (DepthRenderTargetFormat((rb_depth_info >> 16) & 0x1) ==
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DepthRenderTargetFormat::kD24FS8) {
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flags |= DxbcShaderTranslator::kSysFlag_DepthFloat24;
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}
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if (depth_comparison != 0b111 || (rb_depthcontrol & (0x1 | 0x4))) {
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flags |= DxbcShaderTranslator::kSysFlag_DepthStencil;
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flags |= depth_comparison
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if (rb_depthcontrol & 0x2) {
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flags |= ((rb_depthcontrol >> 4) & 0x7)
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<< DxbcShaderTranslator::kSysFlag_DepthPassIfLess_Shift;
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if (DepthRenderTargetFormat((rb_depth_info >> 16) & 0x1) ==
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DepthRenderTargetFormat::kD24FS8) {
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flags |= DxbcShaderTranslator::kSysFlag_DepthFloat24;
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}
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if (rb_depthcontrol & 0x4) {
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flags |= DxbcShaderTranslator::kSysFlag_DepthWriteMask |
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DxbcShaderTranslator::kSysFlag_DepthStencilWrite;
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}
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if (rb_depthcontrol & 0x1) {
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flags |= DxbcShaderTranslator::kSysFlag_StencilTest;
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if (rb_stencilrefmask & (0xFF << 16)) {
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flags |= DxbcShaderTranslator::kSysFlag_DepthStencilWrite;
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}
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} else {
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// In case stencil is used without depth testing - always pass, and
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// don't modify the stored depth.
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flags |= DxbcShaderTranslator::kSysFlag_DepthPassIfLess |
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DxbcShaderTranslator::kSysFlag_DepthPassIfEqual |
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DxbcShaderTranslator::kSysFlag_DepthPassIfGreater;
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}
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if (rb_depthcontrol & 0x1) {
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flags |= DxbcShaderTranslator::kSysFlag_StencilTest;
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if (rb_stencilrefmask & (0xFF << 16)) {
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flags |= DxbcShaderTranslator::kSysFlag_DepthStencilWrite;
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}
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}
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}
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@ -584,10 +584,10 @@ bool PipelineCache::GetCurrentStateDescription(
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uint32_t rb_depthcontrol = regs[XE_GPU_REG_RB_DEPTHCONTROL].u32;
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if (rb_depthcontrol & 0x2) {
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description_out.depth_func = (rb_depthcontrol >> 4) & 0x7;
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description_out.depth_write = (rb_depthcontrol & 0x4) != 0;
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} else {
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description_out.depth_func = 0b111;
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}
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description_out.depth_write = (rb_depthcontrol & 0x4) != 0;
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if (rb_depthcontrol & 0x1) {
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description_out.stencil_enable = 1;
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uint32_t rb_stencilrefmask = regs[XE_GPU_REG_RB_STENCILREFMASK].u32;
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@ -570,8 +570,8 @@ bool RenderTargetCache::UpdateRenderTargets(const D3D12Shader* pixel_shader) {
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}
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uint32_t rb_depthcontrol = regs[XE_GPU_REG_RB_DEPTHCONTROL].u32;
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uint32_t rb_depth_info = regs[XE_GPU_REG_RB_DEPTH_INFO].u32;
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// 0x1 = stencil test, 0x2 = depth test, 0x4 = depth writing.
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enabled[4] = (rb_depthcontrol & (0x1 | 0x2 | 0x4)) != 0;
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// 0x1 = stencil test, 0x2 = depth test.
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enabled[4] = (rb_depthcontrol & (0x1 | 0x2)) != 0;
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edram_bases[4] = std::min(rb_depth_info & 0xFFF, 2048u);
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formats[4] = (rb_depth_info >> 16) & 0x1;
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formats_are_64bpp[4] = false;
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@ -672,7 +672,6 @@ bool RenderTargetCache::UpdateRenderTargets(const D3D12Shader* pixel_shader) {
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const RenderTargetBinding& binding = current_bindings_[i];
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if (binding.is_bound) {
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if (binding.edram_base != edram_bases[i]) {
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full_update = true;
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break;
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}
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if (rov_used) {
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