diff --git a/src/xenia/gpu/d3d12/texture_cache.cc b/src/xenia/gpu/d3d12/texture_cache.cc
index 6f4b5582a..17244c573 100644
--- a/src/xenia/gpu/d3d12/texture_cache.cc
+++ b/src/xenia/gpu/d3d12/texture_cache.cc
@@ -2692,8 +2692,9 @@ bool TextureCache::LoadTextureData(Texture* texture) {
     load_constants.guest_pitch_aligned = level_guest_pitch;
     load_constants.guest_z_stride_block_rows_aligned =
         level_guest_layout.z_slice_stride_block_rows;
-    assert_zero(load_constants.guest_z_stride_block_rows_aligned &
-                (xenos::kTextureTileWidthHeight - 1));
+    assert_true(dimension != xenos::DataDimension::k3D ||
+                !(load_constants.guest_z_stride_block_rows_aligned &
+                  (xenos::kTextureTileWidthHeight - 1)));
 
     uint32_t level_width, level_height, level_depth;
     if (level == level_packed) {
diff --git a/src/xenia/gpu/d3d12/texture_cache.h b/src/xenia/gpu/d3d12/texture_cache.h
index 6e11dddca..5c9c049c4 100644
--- a/src/xenia/gpu/d3d12/texture_cache.h
+++ b/src/xenia/gpu/d3d12/texture_cache.h
@@ -486,7 +486,7 @@ class TextureCache {
     // For tiled textures - row pitch in blocks, aligned to 32.
     // For linear textures - row pitch in bytes.
     uint32_t guest_pitch_aligned;
-    // Must be aligned to 32.
+    // For 3D textures only (ignored otherwise) - aligned to 32.
     uint32_t guest_z_stride_block_rows_aligned;
 
     // vec4 1.
diff --git a/src/xenia/gpu/shaders/texture_load.hlsli b/src/xenia/gpu/shaders/texture_load.hlsli
index 94de4b420..e731b5584 100644
--- a/src/xenia/gpu/shaders/texture_load.hlsli
+++ b/src/xenia/gpu/shaders/texture_load.hlsli
@@ -11,7 +11,7 @@ cbuffer XeTextureLoadConstants : register(b0) {
   // For tiled textures - row pitch in blocks, aligned to 32.
   // For linear textures - row pitch in bytes.
   uint xe_texture_load_guest_pitch_aligned;
-  // Must be aligned to 32.
+  // For 3D textures only (ignored otherwise) - aligned to 32.
   uint xe_texture_load_guest_z_stride_block_rows_aligned;
 
   // If this is a packed mip tail, this is aligned to tile dimensions.