From 894f22cd0bfe4771cc48f56f225da6b0bdd4eec5 Mon Sep 17 00:00:00 2001
From: Ben Vanik <ben.vanik@gmail.com>
Date: Wed, 8 Jan 2014 00:12:22 -0800
Subject: [PATCH] Oh FFS. LOAD_CLOCK.

---
 src/alloy/backend/ivm/ivm_intcode.cc              | 15 +++++++++++++++
 .../backend/x64/lowering/lowering_sequences.cc    |  6 ++++++
 src/alloy/frontend/ppc/ppc_emit_control.cc        |  8 +-------
 src/alloy/hir/hir_builder.cc                      |  8 ++++++++
 src/alloy/hir/hir_builder.h                       |  2 ++
 src/alloy/hir/opcodes.h                           |  2 ++
 src/alloy/hir/opcodes.inl                         |  6 ++++++
 7 files changed, 40 insertions(+), 7 deletions(-)

diff --git a/src/alloy/backend/ivm/ivm_intcode.cc b/src/alloy/backend/ivm/ivm_intcode.cc
index 923cdb621..54873c1a9 100644
--- a/src/alloy/backend/ivm/ivm_intcode.cc
+++ b/src/alloy/backend/ivm/ivm_intcode.cc
@@ -1138,6 +1138,19 @@ int Translate_LOAD_VECTOR_SHR(TranslationContext& ctx, Instr* i) {
   return DispatchToC(ctx, i, IntCode_LOAD_VECTOR_SHR);
 }
 
+uint32_t IntCode_LOAD_CLOCK(IntCodeState& ics, const IntCode* i) {
+  LARGE_INTEGER counter;
+  uint64_t time = 0;
+  if (QueryPerformanceCounter(&counter)) {
+    time = counter.QuadPart;
+  }
+  ics.rf[i->dest_reg].i64 = time;
+  return IA_NEXT;
+}
+int Translate_LOAD_CLOCK(TranslationContext& ctx, Instr* i) {
+  return DispatchToC(ctx, i, IntCode_LOAD_CLOCK);
+}
+
 uint32_t IntCode_LOAD_CONTEXT_I8(IntCodeState& ics, const IntCode* i) {
   ics.rf[i->dest_reg].i8 = *((int8_t*)(ics.context + ics.rf[i->src1_reg].u64));
   DPRINT("%d (%.X) = ctx i8 +%d\n", ics.rf[i->dest_reg].i8, ics.rf[i->dest_reg].u8, ics.rf[i->src1_reg].u64);
@@ -3434,6 +3447,8 @@ static const TranslateFn dispatch_table[] = {
   Translate_LOAD_VECTOR_SHL,
   Translate_LOAD_VECTOR_SHR,
 
+  Translate_LOAD_CLOCK,
+
   Translate_LOAD_CONTEXT,
   Translate_STORE_CONTEXT,
 
diff --git a/src/alloy/backend/x64/lowering/lowering_sequences.cc b/src/alloy/backend/x64/lowering/lowering_sequences.cc
index 0419effa8..052c54439 100644
--- a/src/alloy/backend/x64/lowering/lowering_sequences.cc
+++ b/src/alloy/backend/x64/lowering/lowering_sequences.cc
@@ -230,6 +230,12 @@ void alloy::backend::x64::lowering::RegisterSequences(LoweringTable* table) {
     return true;
   });
 
+  table->AddSequence(OPCODE_LOAD_CLOCK, [](LIRBuilder& lb, Instr*& instr) {
+    // TODO
+    instr = instr->next;
+    return true;
+  });
+
   // --------------------------------------------------------------------------
   // Context
   // --------------------------------------------------------------------------
diff --git a/src/alloy/frontend/ppc/ppc_emit_control.cc b/src/alloy/frontend/ppc/ppc_emit_control.cc
index f4dfcca82..cfc314608 100644
--- a/src/alloy/frontend/ppc/ppc_emit_control.cc
+++ b/src/alloy/frontend/ppc/ppc_emit_control.cc
@@ -498,13 +498,7 @@ XEEMITTER(mfspr,        0x7C0002A6, XFX)(PPCHIRBuilder& f, InstrData& i) {
 }
 
 XEEMITTER(mftb,         0x7C0002E6, XFX)(PPCHIRBuilder& f, InstrData& i) {
-  Value* time;
-  LARGE_INTEGER counter;
-  if (QueryPerformanceCounter(&counter)) {
-    time = f.LoadConstant(counter.QuadPart);
-  } else {
-    time = f.LoadZero(INT64_TYPE);
-  }
+  Value* time = f.LoadClock();
   f.StoreGPR(i.XFX.RT, time);
 
   return 0;
diff --git a/src/alloy/hir/hir_builder.cc b/src/alloy/hir/hir_builder.cc
index 861e70853..f5bd67e81 100644
--- a/src/alloy/hir/hir_builder.cc
+++ b/src/alloy/hir/hir_builder.cc
@@ -848,6 +848,14 @@ Value* HIRBuilder::LoadVectorShr(Value* sh) {
   return i->dest;
 }
 
+Value* HIRBuilder::LoadClock() {
+  Instr* i = AppendInstr(
+      OPCODE_LOAD_CLOCK_info, 0,
+      AllocValue(INT64_TYPE));
+  i->src1.value = i->src2.value = i->src3.value = NULL;
+  return i->dest;
+}
+
 Value* HIRBuilder::LoadContext(size_t offset, TypeName type) {
   Instr* i = AppendInstr(
       OPCODE_LOAD_CONTEXT_info, 0,
diff --git a/src/alloy/hir/hir_builder.h b/src/alloy/hir/hir_builder.h
index 86dd94784..88a193c60 100644
--- a/src/alloy/hir/hir_builder.h
+++ b/src/alloy/hir/hir_builder.h
@@ -117,6 +117,8 @@ public:
   Value* LoadVectorShl(Value* sh);
   Value* LoadVectorShr(Value* sh);
 
+  Value* LoadClock();
+
   Value* LoadContext(size_t offset, TypeName type);
   void StoreContext(size_t offset, Value* value);
 
diff --git a/src/alloy/hir/opcodes.h b/src/alloy/hir/opcodes.h
index abe7f3940..c697f4bbd 100644
--- a/src/alloy/hir/opcodes.h
+++ b/src/alloy/hir/opcodes.h
@@ -101,6 +101,8 @@ enum Opcode {
   OPCODE_LOAD_VECTOR_SHL,
   OPCODE_LOAD_VECTOR_SHR,
 
+  OPCODE_LOAD_CLOCK,
+
   OPCODE_LOAD_CONTEXT,
   OPCODE_STORE_CONTEXT,
 
diff --git a/src/alloy/hir/opcodes.inl b/src/alloy/hir/opcodes.inl
index ef47de819..eb5fd27c6 100644
--- a/src/alloy/hir/opcodes.inl
+++ b/src/alloy/hir/opcodes.inl
@@ -170,6 +170,12 @@ DEFINE_OPCODE(
     OPCODE_SIG_V_V,
     0);
 
+DEFINE_OPCODE(
+    OPCODE_LOAD_CLOCK,
+    "load_clock",
+    OPCODE_SIG_V,
+    0);
+
 DEFINE_OPCODE(
     OPCODE_LOAD_CONTEXT,
     "load_context",