diff --git a/src/xenia/cpu/backend/x64/x64_sequences.cc b/src/xenia/cpu/backend/x64/x64_sequences.cc
index bf04b47dd..563fbfa7c 100644
--- a/src/xenia/cpu/backend/x64/x64_sequences.cc
+++ b/src/xenia/cpu/backend/x64/x64_sequences.cc
@@ -2376,6 +2376,15 @@ struct PREFETCH
 };
 EMITTER_OPCODE_TABLE(OPCODE_PREFETCH, PREFETCH);
 
+// ============================================================================
+// OPCODE_MEMORY_BARRIER
+// ============================================================================
+struct MEMORY_BARRIER
+    : Sequence<MEMORY_BARRIER, I<OPCODE_MEMORY_BARRIER, VoidOp>> {
+  static void Emit(X64Emitter& e, const EmitArgType& i) { e.mfence(); }
+};
+EMITTER_OPCODE_TABLE(OPCODE_MEMORY_BARRIER, MEMORY_BARRIER);
+
 // ============================================================================
 // OPCODE_MEMSET
 // ============================================================================
@@ -7056,6 +7065,7 @@ void RegisterSequences() {
   Register_OPCODE_STORE();
   Register_OPCODE_MEMSET();
   Register_OPCODE_PREFETCH();
+  Register_OPCODE_MEMORY_BARRIER();
   Register_OPCODE_MAX();
   Register_OPCODE_VECTOR_MAX();
   Register_OPCODE_MIN();
diff --git a/src/xenia/cpu/frontend/ppc_emit_memory.cc b/src/xenia/cpu/frontend/ppc_emit_memory.cc
index caef9fafe..64bfdf908 100644
--- a/src/xenia/cpu/frontend/ppc_emit_memory.cc
+++ b/src/xenia/cpu/frontend/ppc_emit_memory.cc
@@ -658,14 +658,12 @@ XEEMITTER(stswx, 0x7C00052A, X)(PPCHIRBuilder& f, InstrData& i) {
 // Memory synchronization (A-18)
 
 XEEMITTER(eieio, 0x7C0006AC, X)(PPCHIRBuilder& f, InstrData& i) {
-  // XEINSTRNOTIMPLEMENTED();
-  f.Nop();
+  f.MemoryBarrier();
   return 0;
 }
 
 XEEMITTER(sync, 0x7C0004AC, X)(PPCHIRBuilder& f, InstrData& i) {
-  // XEINSTRNOTIMPLEMENTED();
-  f.Nop();
+  f.MemoryBarrier();
   return 0;
 }
 
diff --git a/src/xenia/cpu/hir/hir_builder.cc b/src/xenia/cpu/hir/hir_builder.cc
index 9a27c3aaf..e93cb7c90 100644
--- a/src/xenia/cpu/hir/hir_builder.cc
+++ b/src/xenia/cpu/hir/hir_builder.cc
@@ -1263,6 +1263,8 @@ void HIRBuilder::Prefetch(Value* address, size_t length,
   i->src3.value = NULL;
 }
 
+void HIRBuilder::MemoryBarrier() { AppendInstr(OPCODE_MEMORY_BARRIER_info, 0); }
+
 Value* HIRBuilder::Max(Value* value1, Value* value2) {
   ASSERT_TYPES_EQUAL(value1, value2);
 
diff --git a/src/xenia/cpu/hir/hir_builder.h b/src/xenia/cpu/hir/hir_builder.h
index fb4ad489a..59090f668 100644
--- a/src/xenia/cpu/hir/hir_builder.h
+++ b/src/xenia/cpu/hir/hir_builder.h
@@ -150,6 +150,7 @@ class HIRBuilder {
   void Store(Value* address, Value* value, uint32_t store_flags = 0);
   void Memset(Value* address, Value* value, Value* length);
   void Prefetch(Value* address, size_t length, uint32_t prefetch_flags = 0);
+  void MemoryBarrier();
 
   Value* Max(Value* value1, Value* value2);
   Value* VectorMax(Value* value1, Value* value2, TypeName part_type,
diff --git a/src/xenia/cpu/hir/opcodes.h b/src/xenia/cpu/hir/opcodes.h
index 83b6a77a6..0fd952cbe 100644
--- a/src/xenia/cpu/hir/opcodes.h
+++ b/src/xenia/cpu/hir/opcodes.h
@@ -154,6 +154,7 @@ enum Opcode {
   OPCODE_STORE,
   OPCODE_MEMSET,
   OPCODE_PREFETCH,
+  OPCODE_MEMORY_BARRIER,
   OPCODE_MAX,
   OPCODE_VECTOR_MAX,
   OPCODE_MIN,
diff --git a/src/xenia/cpu/hir/opcodes.inl b/src/xenia/cpu/hir/opcodes.inl
index 68d182223..c7c8b6f67 100644
--- a/src/xenia/cpu/hir/opcodes.inl
+++ b/src/xenia/cpu/hir/opcodes.inl
@@ -241,13 +241,19 @@ DEFINE_OPCODE(
     OPCODE_MEMSET,
     "memset",
     OPCODE_SIG_X_V_V_V,
-    0)
+    OPCODE_FLAG_MEMORY)
 
 DEFINE_OPCODE(
     OPCODE_PREFETCH,
     "prefetch",
     OPCODE_SIG_X_V_O,
-    0)
+    OPCODE_FLAG_MEMORY)
+
+DEFINE_OPCODE(
+    OPCODE_MEMORY_BARRIER,
+    "memory_barrier",
+    OPCODE_SIG_X,
+    OPCODE_FLAG_MEMORY | OPCODE_FLAG_VOLATILE)
 
 DEFINE_OPCODE(
     OPCODE_MAX,