lvebx/lvehx/lvewx.

src/alloy/frontend/ppc/ppc_emit_altivec.cc

@@ -83,19 +83,25 @@ XEEMITTER(dss, 0x7C00066C, XDSS)(PPCHIRBuilder& f, InstrData& i) {
 }
 
 XEEMITTER(lvebx, 0x7C00000E, X)(PPCHIRBuilder& f, InstrData& i) {
-  XEINSTRNOTIMPLEMENTED();
-  return 1;
+  // Same as lvx.
+  Value* ea = f.And(CalculateEA_0(f, i.X.RA, i.X.RB), f.LoadConstant(~0xFull));
+  f.StoreVR(i.X.RT, f.ByteSwap(f.Load(ea, VEC128_TYPE)));
+  return 0;
 }
 
 XEEMITTER(lvehx, 0x7C00004E, X)(PPCHIRBuilder& f, InstrData& i) {
-  XEINSTRNOTIMPLEMENTED();
-  return 1;
+  // Same as lvx.
+  Value* ea = f.And(CalculateEA_0(f, i.X.RA, i.X.RB), f.LoadConstant(~0xFull));
+  f.StoreVR(i.X.RT, f.ByteSwap(f.Load(ea, VEC128_TYPE)));
+  return 0;
 }
 
 int InstrEmit_lvewx_(PPCHIRBuilder& f, InstrData& i, uint32_t vd, uint32_t ra,
                      uint32_t rb) {
-  XEINSTRNOTIMPLEMENTED();
-  return 1;
+  // Same as lvx.
+  Value* ea = f.And(CalculateEA_0(f, ra, rb), f.LoadConstant(~0xFull));
+  f.StoreVR(vd, f.ByteSwap(f.Load(ea, VEC128_TYPE)));
+  return 0;
 }
 XEEMITTER(lvewx, 0x7C00008E, X)(PPCHIRBuilder& f, InstrData& i) {
   return InstrEmit_lvewx_(f, i, i.X.RT, i.X.RA, i.X.RB);

src/alloy/frontend/ppc/test/bin/instr_lvexx.dis

@@ -0,0 +1,29 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_lvexx.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_lvebx_1>:
+  100000:	7c 60 20 0e 	lvebx   v3,0,r4
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_lvebx_2>:
+  100008:	7c 60 20 0e 	lvebx   v3,0,r4
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_lvehx_1>:
+  100010:	7c 60 20 4e 	lvehx   v3,0,r4
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_lvehx_2>:
+  100018:	7c 60 20 4e 	lvehx   v3,0,r4
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_lvewx_1>:
+  100020:	7c 60 20 8e 	lvewx   v3,0,r4
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_lvewx_2>:
+  100028:	7c 60 20 8e 	lvewx   v3,0,r4
+  10002c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_lvexx.map

@@ -0,0 +1,6 @@
+0000000000000000 t test_lvebx_1
+0000000000000008 t test_lvebx_2
+0000000000000010 t test_lvehx_1
+0000000000000018 t test_lvehx_2
+0000000000000020 t test_lvewx_1
+0000000000000028 t test_lvewx_2

src/alloy/frontend/ppc/test/instr_lvexx.s

@@ -0,0 +1,47 @@
+test_lvebx_1:
+  #_ MEMORY_IN 00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  #_ REGISTER_IN r4 0
+  lvebx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvebx_2:
+  #_ MEMORY_IN 00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  #_ REGISTER_IN r4 4
+  lvebx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 4
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvehx_1:
+  #_ MEMORY_IN 00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  #_ REGISTER_IN r4 0
+  lvehx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvehx_2:
+  #_ MEMORY_IN 00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  #_ REGISTER_IN r4 4
+  lvehx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 4
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvewx_1:
+  #_ MEMORY_IN 00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  #_ REGISTER_IN r4 0
+  lvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
+
+test_lvewx_2:
+  #_ MEMORY_IN 00000000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
+  #_ REGISTER_IN r4 4
+  lvewx v3, r0, r4
+  blr
+  #_ REGISTER_OUT r4 4
+  #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]