Xenos: Add a few bitfield registers to registers.h
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Dr. Chat
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/**
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******************************************************************************
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* Xenia : Xbox 360 Emulator Research Project *
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******************************************************************************
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* Copyright 2017 Ben Vanik. All rights reserved. *
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* Released under the BSD license - see LICENSE in the root for more details. *
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******************************************************************************
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*/
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#ifndef XENIA_GPU_REGISTERS_H_
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#define XENIA_GPU_REGISTERS_H_
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#include <cstdint>
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#include <cstdlib>
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#include "xenia/base/bit_field.h"
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#include "xenia/gpu/xenos.h"
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// Most registers can be found from:
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// https://github.com/UDOOboard/Kernel_Unico/blob/master/drivers/mxc/amd-gpu/include/reg/yamato/14/yamato_registers.h
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namespace xe {
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namespace gpu {
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namespace reg {
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/**************************************************
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___ ___ _ _ _____ ___ ___ _
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/ __/ _ \| \| |_ _| _ \/ _ \| |
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| (_| (_) | .` | | | | / (_) | |__
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\___\___/|_|\_| |_| |_|_\\___/|____|
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***************************************************/
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union WAIT_UNTIL {
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xe::bf<uint32_t, 1, 1> wait_re_vsync;
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xe::bf<uint32_t, 2, 1> wait_fe_vsync;
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xe::bf<uint32_t, 3, 1> wait_vsync;
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xe::bf<uint32_t, 4, 1> wait_dsply_id0;
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xe::bf<uint32_t, 5, 1> wait_dsply_id1;
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xe::bf<uint32_t, 6, 1> wait_dsply_id2;
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xe::bf<uint32_t, 10, 1> wait_cmdfifo;
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xe::bf<uint32_t, 14, 1> wait_2d_idle;
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xe::bf<uint32_t, 15, 1> wait_3d_idle;
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xe::bf<uint32_t, 16, 1> wait_2d_idleclean;
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xe::bf<uint32_t, 17, 1> wait_3d_idleclean;
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xe::bf<uint32_t, 20, 4> cmdfifo_entries;
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uint32_t value;
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};
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/**************************************************
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___ ___ ___ __ __ ___ _____ _____ _____
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| _ \ _ \_ _| \/ |_ _|_ _|_ _\ \ / / __|
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| _/ /| || |\/| || | | | | | \ V /| _|
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|_| |_|_\___|_| |_|___| |_| |___| \_/ |___|
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_ ___ ___ ___ __ __ ___ _ ___ ___
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/_\ / __/ __| __| \/ | _ ) | | __| _ \
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/ _ \\__ \__ \ _|| |\/| | _ \ |__| _|| /
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/_/ \_\___/___/___|_| |_|___/____|___|_|_\
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***************************************************/
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// Setup Unit / Scanline Converter mode cntl
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union PA_SU_SC_MODE_CNTL {
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xe::bf<uint32_t, 0, 1> cull_front;
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xe::bf<uint32_t, 1, 1> cull_back;
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xe::bf<uint32_t, 2, 1> face;
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xe::bf<uint32_t, 3, 2> poly_mode;
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xe::bf<uint32_t, 5, 3> polymode_front_ptype;
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xe::bf<uint32_t, 8, 3> polymode_back_ptype;
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xe::bf<uint32_t, 11, 1> poly_offset_front_enable;
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xe::bf<uint32_t, 12, 1> poly_offset_back_enable;
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xe::bf<uint32_t, 13, 1> poly_offset_para_enable;
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xe::bf<uint32_t, 15, 1> msaa_enable;
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xe::bf<uint32_t, 16, 1> vtx_window_offset_enable;
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xe::bf<uint32_t, 18, 1> line_stipple_enable;
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xe::bf<uint32_t, 19, 1> provoking_vtx_last;
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xe::bf<uint32_t, 20, 1> persp_corr_dis;
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xe::bf<uint32_t, 21, 1> multi_prim_ib_ena;
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xe::bf<uint32_t, 23, 1> quad_order_enable;
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xe::bf<uint32_t, 25, 1> wait_rb_idle_all_tri;
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xe::bf<uint32_t, 26, 1> wait_rb_idle_first_tri_new_state;
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uint32_t value;
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};
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// Scanline converter viz query
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union PA_SC_VIZ_QUERY {
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xe::bf<uint32_t, 0, 1> viz_query_ena;
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xe::bf<uint32_t, 1, 5> viz_query_id;
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xe::bf<uint32_t, 7, 1> kill_pix_post_early_z;
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uint32_t value;
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};
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// Clipper clip control
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// TODO(DrChat): This seem to differ. Need to examine this.
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// https://github.com/decaf-emu/decaf-emu/blob/c017a9ff8128852fb9a5da19466778a171cea6e1/src/libdecaf/src/gpu/latte_registers_pa.h#L11
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union PA_CL_CLIP_CNTL {
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xe::bf<uint32_t, 0, 1> ucp_ena_0;
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xe::bf<uint32_t, 1, 1> ucp_ena_1;
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xe::bf<uint32_t, 2, 1> ucp_ena_2;
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xe::bf<uint32_t, 3, 1> ucp_ena_3;
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xe::bf<uint32_t, 4, 1> ucp_ena_4;
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xe::bf<uint32_t, 5, 1> ucp_ena_5;
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xe::bf<uint32_t, 16, 1> clip_disable;
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xe::bf<uint32_t, 18, 1> boundary_edge_flag_ena;
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xe::bf<uint32_t, 19, 1> dx_clip_space_def;
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xe::bf<uint32_t, 20, 1> dis_clip_err_detect;
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xe::bf<uint32_t, 21, 1> vtx_kill_or;
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xe::bf<uint32_t, 22, 1> xy_nan_retain;
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xe::bf<uint32_t, 23, 1> z_nan_retain;
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xe::bf<uint32_t, 24, 1> w_nan_retain;
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uint32_t value;
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};
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// Viewport transform engine control
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union PA_CL_VTE_CNTL {
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xe::bf<uint32_t, 0, 1> vport_x_scale_ena;
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xe::bf<uint32_t, 1, 1> vport_x_offset_ena;
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xe::bf<uint32_t, 2, 1> vport_y_scale_ena;
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xe::bf<uint32_t, 3, 1> vport_y_offset_ena;
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xe::bf<uint32_t, 4, 1> vport_z_scale_ena;
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xe::bf<uint32_t, 5, 1> vport_z_offset_ena;
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xe::bf<uint32_t, 8, 1> vtx_xy_fmt;
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xe::bf<uint32_t, 9, 1> vtx_z_fmt;
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xe::bf<uint32_t, 10, 1> vtx_w0_fmt;
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xe::bf<uint32_t, 11, 1> perfcounter_ref;
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uint32_t value;
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};
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/**************************************************
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___ ___
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| _ \ _ )
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| / _ \
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|_|_\___/
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***************************************************/
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union RB_MODECONTROL {
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xe::bf<xenos::ModeControl, 0, 3> edram_mode;
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uint32_t value;
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};
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union RB_SURFACE_INFO {
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xe::bf<uint32_t, 0, 14> surface_pitch;
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xe::bf<MsaaSamples, 14, 2> msaa_samples;
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xe::bf<uint32_t, 16, 14> hiz_pitch;
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uint32_t value;
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};
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union RB_COLORCONTROL {
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xe::bf<uint32_t, 0, 3> alpha_func;
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xe::bf<uint32_t, 3, 1> alpha_test_enable;
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xe::bf<uint32_t, 4, 1> alpha_to_mask_enable;
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xe::bf<uint32_t, 5, 1> blend_disable;
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xe::bf<uint32_t, 6, 1> fog_enable;
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xe::bf<uint32_t, 7, 1> vs_exports_fog;
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xe::bf<uint32_t, 8, 4> rop_code;
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xe::bf<uint32_t, 12, 2> dither_mode;
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xe::bf<uint32_t, 14, 2> dither_type;
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xe::bf<uint32_t, 16, 1> pixel_fog;
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xe::bf<uint32_t, 24, 2> alpha_to_mask_offset0;
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xe::bf<uint32_t, 26, 2> alpha_to_mask_offset1;
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xe::bf<uint32_t, 28, 2> alpha_to_mask_offset2;
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xe::bf<uint32_t, 30, 2> alpha_to_mask_offset3;
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uint32_t value;
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};
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union RB_COLOR_INFO {
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xe::bf<uint32_t, 0, 12> color_base;
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xe::bf<ColorRenderTargetFormat, 16, 4> color_format;
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xe::bf<uint32_t, 22, 1> unk_22;
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uint32_t value;
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};
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union RB_DEPTH_INFO {
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xe::bf<uint32_t, 0, 12> depth_base;
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xe::bf<DepthRenderTargetFormat, 16, 1> depth_format;
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uint32_t value;
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};
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} // namespace reg
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} // namespace gpu
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} // namespace xe
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#endif // XENIA_GPU_REGISTERS_H_
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@ -554,9 +554,9 @@ enum Type3Opcode {
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PM4_VIZ_QUERY = 0x23, // begin/end initiator for viz query extent processing
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PM4_SET_STATE = 0x25, // fetch state sub-blocks and initiate shader code DMAs
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PM4_SET_CONSTANT = 0x2d, // load constant into chip and to memory
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PM4_SET_CONSTANT2 = 0x55,
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PM4_SET_CONSTANT2 = 0x55, // INCR_UPDATE_STATE
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PM4_SET_SHADER_CONSTANTS = 0x56, // INCR_UPDT_CONST
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PM4_LOAD_ALU_CONSTANT = 0x2f, // load constants from memory
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PM4_SET_SHADER_CONSTANTS = 0x56, // ?? constant values
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PM4_IM_LOAD = 0x27, // load sequencer instruction memory (pointer-based)
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PM4_IM_LOAD_IMMEDIATE = 0x2b, // load sequencer instruction memory (code embedded in packet)
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PM4_LOAD_CONSTANT_CONTEXT = 0x2e, // load constants from a location in memory
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