From 760d82a9af3c13d973c1b5fceb770162021b2b66 Mon Sep 17 00:00:00 2001 From: Ben Vanik Date: Sun, 8 Dec 2013 14:31:03 -0800 Subject: [PATCH] Fixing endianess of register load/store. --- src/alloy/backend/ivm/ivm_intcode.cc | 28 ++++++++++++++-------------- 1 file changed, 14 insertions(+), 14 deletions(-) diff --git a/src/alloy/backend/ivm/ivm_intcode.cc b/src/alloy/backend/ivm/ivm_intcode.cc index 0437c1d40..8c530a14c 100644 --- a/src/alloy/backend/ivm/ivm_intcode.cc +++ b/src/alloy/backend/ivm/ivm_intcode.cc @@ -174,21 +174,21 @@ uint32_t IntCode_LOAD_REGISTER_I16(IntCodeState& ics, const IntCode* i) { uint64_t address = ics.rf[i->src1_reg].u32; RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*) (i->src2_reg | ((uint64_t)i->src3_reg << 32)); - ics.rf[i->dest_reg].i16 = (int16_t)cbs->read(cbs->context, address); + ics.rf[i->dest_reg].i16 = XESWAP16((int16_t)cbs->read(cbs->context, address)); return IA_NEXT; } uint32_t IntCode_LOAD_REGISTER_I32(IntCodeState& ics, const IntCode* i) { uint64_t address = ics.rf[i->src1_reg].u32; RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*) (i->src2_reg | ((uint64_t)i->src3_reg << 32)); - ics.rf[i->dest_reg].i32 = (int32_t)cbs->read(cbs->context, address); + ics.rf[i->dest_reg].i32 = XESWAP32((int32_t)cbs->read(cbs->context, address)); return IA_NEXT; } uint32_t IntCode_LOAD_REGISTER_I64(IntCodeState& ics, const IntCode* i) { uint64_t address = ics.rf[i->src1_reg].u32; RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*) (i->src2_reg | ((uint64_t)i->src3_reg << 32)); - ics.rf[i->dest_reg].i64 = (int64_t)cbs->read(cbs->context, address); + ics.rf[i->dest_reg].i64 = XESWAP64((int64_t)cbs->read(cbs->context, address)); return IA_NEXT; } int DispatchRegisterRead( @@ -233,7 +233,7 @@ uint32_t IntCode_LOAD_REGISTER_I16_DYNAMIC(IntCodeState& ics, const IntCode* i) RegisterAccessCallbacks* cbs = ics.access_callbacks; while (cbs) { if (cbs->handles(cbs->context, address)) { - ics.rf[i->dest_reg].i16 = (int16_t)cbs->read(cbs->context, address); + ics.rf[i->dest_reg].i16 = XESWAP16((int16_t)cbs->read(cbs->context, address)); return IA_NEXT; } cbs = cbs->next; @@ -245,7 +245,7 @@ uint32_t IntCode_LOAD_REGISTER_I32_DYNAMIC(IntCodeState& ics, const IntCode* i) RegisterAccessCallbacks* cbs = ics.access_callbacks; while (cbs) { if (cbs->handles(cbs->context, address)) { - ics.rf[i->dest_reg].i32 = (int32_t)cbs->read(cbs->context, address); + ics.rf[i->dest_reg].i32 = XESWAP32((int32_t)cbs->read(cbs->context, address)); return IA_NEXT; } cbs = cbs->next; @@ -257,7 +257,7 @@ uint32_t IntCode_LOAD_REGISTER_I64_DYNAMIC(IntCodeState& ics, const IntCode* i) RegisterAccessCallbacks* cbs = ics.access_callbacks; while (cbs) { if (cbs->handles(cbs->context, address)) { - ics.rf[i->dest_reg].i64 = (int64_t)cbs->read(cbs->context, address); + ics.rf[i->dest_reg].i64 = XESWAP64((int64_t)cbs->read(cbs->context, address)); return IA_NEXT; } cbs = cbs->next; @@ -269,28 +269,28 @@ uint32_t IntCode_STORE_REGISTER_I8(IntCodeState& ics, const IntCode* i) { uint64_t address = ics.rf[i->src1_reg].u32; RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*) (i->src3_reg | ((uint64_t)i->dest_reg << 32)); - cbs->write(cbs->context, address, ics.rf[i->src2_reg].i64 & 0xFF); + cbs->write(cbs->context, address, ics.rf[i->src2_reg].i8); return IA_NEXT; } uint32_t IntCode_STORE_REGISTER_I16(IntCodeState& ics, const IntCode* i) { uint64_t address = ics.rf[i->src1_reg].u32; RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*) (i->src3_reg | ((uint64_t)i->dest_reg << 32)); - cbs->write(cbs->context, address, ics.rf[i->src2_reg].i64 & 0xFFFF); + cbs->write(cbs->context, address, XESWAP16(ics.rf[i->src2_reg].i16)); return IA_NEXT; } uint32_t IntCode_STORE_REGISTER_I32(IntCodeState& ics, const IntCode* i) { uint64_t address = ics.rf[i->src1_reg].u32; RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*) (i->src3_reg | ((uint64_t)i->dest_reg << 32)); - cbs->write(cbs->context, address, ics.rf[i->src2_reg].i64 & 0xFFFFFFFF); + cbs->write(cbs->context, address, XESWAP32(ics.rf[i->src2_reg].i32)); return IA_NEXT; } uint32_t IntCode_STORE_REGISTER_I64(IntCodeState& ics, const IntCode* i) { uint64_t address = ics.rf[i->src1_reg].u32; RegisterAccessCallbacks* cbs = (RegisterAccessCallbacks*) (i->src3_reg | ((uint64_t)i->dest_reg << 32)); - cbs->write(cbs->context, address, ics.rf[i->src2_reg].i64); + cbs->write(cbs->context, address, XESWAP64(ics.rf[i->src2_reg].i64)); return IA_NEXT; } int DispatchRegisterWrite( @@ -323,7 +323,7 @@ uint32_t IntCode_STORE_REGISTER_I8_DYNAMIC(IntCodeState& ics, const IntCode* i) RegisterAccessCallbacks* cbs = ics.access_callbacks; while (cbs) { if (cbs->handles(cbs->context, address)) { - cbs->write(cbs->context, address, ics.rf[i->src2_reg].i64 & 0xFF); + cbs->write(cbs->context, address, ics.rf[i->src2_reg].i8); return IA_NEXT; } cbs = cbs->next; @@ -335,7 +335,7 @@ uint32_t IntCode_STORE_REGISTER_I16_DYNAMIC(IntCodeState& ics, const IntCode* i) RegisterAccessCallbacks* cbs = ics.access_callbacks; while (cbs) { if (cbs->handles(cbs->context, address)) { - cbs->write(cbs->context, address, ics.rf[i->src2_reg].i64 & 0xFFFF); + cbs->write(cbs->context, address, XESWAP16(ics.rf[i->src2_reg].i16)); return IA_NEXT; } cbs = cbs->next; @@ -347,7 +347,7 @@ uint32_t IntCode_STORE_REGISTER_I32_DYNAMIC(IntCodeState& ics, const IntCode* i) RegisterAccessCallbacks* cbs = ics.access_callbacks; while (cbs) { if (cbs->handles(cbs->context, address)) { - cbs->write(cbs->context, address, ics.rf[i->src2_reg].i64 & 0xFFFFFFFF); + cbs->write(cbs->context, address, XESWAP32(ics.rf[i->src2_reg].i32)); return IA_NEXT; } cbs = cbs->next; @@ -359,7 +359,7 @@ uint32_t IntCode_STORE_REGISTER_I64_DYNAMIC(IntCodeState& ics, const IntCode* i) RegisterAccessCallbacks* cbs = ics.access_callbacks; while (cbs) { if (cbs->handles(cbs->context, address)) { - cbs->write(cbs->context, address, ics.rf[i->src2_reg].i64); + cbs->write(cbs->context, address, XESWAP64(ics.rf[i->src2_reg].i64)); return IA_NEXT; } cbs = cbs->next;