From 6e2bf0b4b129d9b7dac75aeabbe55a16e75b3dea Mon Sep 17 00:00:00 2001 From: "Dr. Chat" Date: Sat, 13 May 2017 23:12:53 -0500 Subject: [PATCH] Native test runner: Support FPSCR --- src/xenia/cpu/ppc/testing/ppc_testing_native_main.cc | 1 + src/xenia/cpu/ppc/testing/ppc_testing_native_thunks.s | 8 +++++++- 2 files changed, 8 insertions(+), 1 deletion(-) diff --git a/src/xenia/cpu/ppc/testing/ppc_testing_native_main.cc b/src/xenia/cpu/ppc/testing/ppc_testing_native_main.cc index 04d950433..28ba3887b 100644 --- a/src/xenia/cpu/ppc/testing/ppc_testing_native_main.cc +++ b/src/xenia/cpu/ppc/testing/ppc_testing_native_main.cc @@ -37,6 +37,7 @@ struct Context { double f[32]; // 0x100 vec128_t v[32]; // 0x200 For now, only support 32 vector registers. uint32_t cr; // 0x400 Condition register + uint64_t fpscr; // 0x404 FPSCR }; typedef std::vector> AnnotationList; diff --git a/src/xenia/cpu/ppc/testing/ppc_testing_native_thunks.s b/src/xenia/cpu/ppc/testing/ppc_testing_native_thunks.s index 006ae8359..a52982ab3 100644 --- a/src/xenia/cpu/ppc/testing/ppc_testing_native_thunks.s +++ b/src/xenia/cpu/ppc/testing/ppc_testing_native_thunks.s @@ -10,9 +10,12 @@ # r3 = context # this does not touch r1, r3, r4, r13 .load_registers_ctx: - lwz r2, 0x400(r3) # CR + lwz r2, 0x400(r3) # CR mtcrf 0xFF, r2 + lfd f0, 0x404(r3) # FPSCR + mtfsf 0xFF, f0 + li r2, 0 mtxer r2 @@ -286,6 +289,9 @@ mfcr r2 # CR stw r2, 0x400(r3) + + mffs f0 # FPSCR + stfd f0, 0x404(r3) blr # void xe_call_native(Context* ctx, void* func)