diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicl.bin b/src/alloy/frontend/ppc/test/bin/instr_rldicl.bin new file mode 100644 index 000000000..4ff0f0586 Binary files /dev/null and b/src/alloy/frontend/ppc/test/bin/instr_rldicl.bin differ diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicl.dis b/src/alloy/frontend/ppc/test/bin/instr_rldicl.dis new file mode 100644 index 000000000..d3dc12986 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_rldicl.dis @@ -0,0 +1,41 @@ + +/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_rldicl.o: file format elf64-powerpc + + +Disassembly of section .text: + +0000000000100000 : + 100000: 78 83 c0 00 rotldi r3,r4,24 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 78 83 c2 00 rldicl r3,r4,24,8 + 10000c: 4e 80 00 20 blr + +0000000000100010 : + 100010: 78 83 c7 e0 rldicl r3,r4,24,63 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 78 83 00 00 rotldi r3,r4,0 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 78 83 07 e0 clrldi r3,r4,63 + 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 78 83 02 00 clrldi r3,r4,8 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 78 83 f8 02 rotldi r3,r4,63 + 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 78 83 ff e2 rldicl r3,r4,63,63 + 10003c: 4e 80 00 20 blr + +0000000000100040 : + 100040: 78 83 f8 00 rotldi r3,r4,31 + 100044: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicl.map b/src/alloy/frontend/ppc/test/bin/instr_rldicl.map new file mode 100644 index 000000000..6bc8f0d85 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_rldicl.map @@ -0,0 +1,9 @@ +0000000000000000 t test_rldicl_1 +0000000000000008 t test_rldicl_2 +0000000000000010 t test_rldicl_3 +0000000000000018 t test_rldicl_4 +0000000000000020 t test_rldicl_5 +0000000000000028 t test_rldicl_6 +0000000000000030 t test_rldicl_7 +0000000000000038 t test_rldicl_8 +0000000000000040 t test_rldicl_9 diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicr.bin b/src/alloy/frontend/ppc/test/bin/instr_rldicr.bin new file mode 100644 index 000000000..cf03dfbfc Binary files /dev/null and b/src/alloy/frontend/ppc/test/bin/instr_rldicr.bin differ diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicr.dis b/src/alloy/frontend/ppc/test/bin/instr_rldicr.dis new file mode 100644 index 000000000..7487f0ee5 --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_rldicr.dis @@ -0,0 +1,41 @@ + +/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_rldicr.o: file format elf64-powerpc + + +Disassembly of section .text: + +0000000000100000 : + 100000: 78 83 c0 04 rldicr r3,r4,24,0 + 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 78 83 c2 04 rldicr r3,r4,24,8 + 10000c: 4e 80 00 20 blr + +0000000000100010 : + 100010: 78 83 c7 e4 rldicr r3,r4,24,63 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 78 83 00 04 rldicr r3,r4,0,0 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 78 83 07 e4 rldicr r3,r4,0,63 + 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 78 83 02 04 rldicr r3,r4,0,8 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 78 83 f8 06 rldicr r3,r4,63,0 + 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 78 83 ff e6 rldicr r3,r4,63,63 + 10003c: 4e 80 00 20 blr + +0000000000100040 : + 100040: 78 83 f8 04 rldicr r3,r4,31,0 + 100044: 4e 80 00 20 blr diff --git a/src/alloy/frontend/ppc/test/bin/instr_rldicr.map b/src/alloy/frontend/ppc/test/bin/instr_rldicr.map new file mode 100644 index 000000000..93ee471fc --- /dev/null +++ b/src/alloy/frontend/ppc/test/bin/instr_rldicr.map @@ -0,0 +1,9 @@ +0000000000000000 t test_rldicr_1 +0000000000000008 t test_rldicr_2 +0000000000000010 t test_rldicr_3 +0000000000000018 t test_rldicr_4 +0000000000000020 t test_rldicr_5 +0000000000000028 t test_rldicr_6 +0000000000000030 t test_rldicr_7 +0000000000000038 t test_rldicr_8 +0000000000000040 t test_rldicr_9 diff --git a/src/alloy/frontend/ppc/test/instr_rldicl.s b/src/alloy/frontend/ppc/test/instr_rldicl.s new file mode 100644 index 000000000..c23d8554b --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_rldicl.s @@ -0,0 +1,62 @@ +test_rldicl_1: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicl r3, r4, 24, 0 + blr + #_ REGISTER_OUT r3 0x6789abcdef012345 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_rldicl_2: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicl r3, r4, 24, 8 + blr + #_ REGISTER_OUT r3 0x0089abcdef012345 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_rldicl_3: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicl r3, r4, 24, 63 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_rldicl_4: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicl r3, r4, 0, 0 + blr + #_ REGISTER_OUT r3 0x0123456789abcdef + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_rldicl_5: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicl r3, r4, 0, 63 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_rldicl_6: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicl r3, r4, 0, 8 + blr + #_ REGISTER_OUT r3 0x0023456789abcdef + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_rldicl_7: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicl r3, r4, 63, 0 + blr + #_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_rldicl_8: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicl r3, r4, 63, 63 + blr + #_ REGISTER_OUT r3 0x0000000000000001 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_rldicl_9: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicl r3, r4, 31, 0 + blr + #_ REGISTER_OUT r3 0xc4d5e6f78091a2b3 + #_ REGISTER_OUT r4 0x0123456789ABCDEF diff --git a/src/alloy/frontend/ppc/test/instr_rldicr.s b/src/alloy/frontend/ppc/test/instr_rldicr.s new file mode 100644 index 000000000..7380eca31 --- /dev/null +++ b/src/alloy/frontend/ppc/test/instr_rldicr.s @@ -0,0 +1,62 @@ +test_rldicr_1: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicr r3, r4, 24, 0 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_rldicr_2: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicr r3, r4, 24, 8 + blr + #_ REGISTER_OUT r3 0x6780000000000000 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_rldicr_3: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicr r3, r4, 24, 63 + blr + #_ REGISTER_OUT r3 0x6789abcdef012345 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_rldicr_4: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicr r3, r4, 0, 0 + blr + #_ REGISTER_OUT r3 0x0000000000000000 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_rldicr_5: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicr r3, r4, 0, 63 + blr + #_ REGISTER_OUT r3 0x0123456789abcdef + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_rldicr_6: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicr r3, r4, 0, 8 + blr + #_ REGISTER_OUT r3 0x0100000000000000 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_rldicr_7: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicr r3, r4, 63, 0 + blr + #_ REGISTER_OUT r3 0x8000000000000000 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_rldicr_8: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicr r3, r4, 63, 63 + blr + #_ REGISTER_OUT r3 0x8091a2b3c4d5e6f7 + #_ REGISTER_OUT r4 0x0123456789ABCDEF + +test_rldicr_9: + #_ REGISTER_IN r4 0x0123456789ABCDEF + rldicr r3, r4, 31, 0 + blr + #_ REGISTER_OUT r3 0x8000000000000000 + #_ REGISTER_OUT r4 0x0123456789ABCDEF