diff --git a/src/xenia/cpu/ppc/ppc_emit_fpu.cc b/src/xenia/cpu/ppc/ppc_emit_fpu.cc
index 70e01cd80..8fe94da5a 100644
--- a/src/xenia/cpu/ppc/ppc_emit_fpu.cc
+++ b/src/xenia/cpu/ppc/ppc_emit_fpu.cc
@@ -303,7 +303,19 @@ int InstrEmit_fcmpx_(PPCHIRBuilder& f, const InstrData& i, bool ordered) {
   // TODO(benvanik): update FPCC for mffsx/etc
   // TODO(benvanik): update VXSNAN
   const uint32_t crf = i.X.RT >> 2;
-  f.UpdateCR(crf, f.LoadFPR(i.X.RA), f.LoadFPR(i.X.RB));
+  Value* ra = f.LoadFPR(i.X.RA);
+  Value* rb = f.LoadFPR(i.X.RB);
+
+  Value* nan = f.Or(f.IsNan(ra), f.IsNan(rb));
+  f.StoreContext(offsetof(PPCContext, cr0) + (4 * crf) + 3, nan);
+  Value* not_nan = f.Xor(nan, f.LoadConstantInt8(0x01));
+
+  Value* lt = f.And(not_nan, f.CompareSLT(ra, rb));
+  f.StoreContext(offsetof(PPCContext, cr0) + (4 * crf) + 0, lt);
+  Value* gt = f.And(not_nan, f.CompareSGT(ra, rb));
+  f.StoreContext(offsetof(PPCContext, cr0) + (4 * crf) + 1, gt);
+  Value* eq = f.And(not_nan, f.CompareEQ(ra, rb));
+  f.StoreContext(offsetof(PPCContext, cr0) + (4 * crf) + 2, eq);
   return 0;
 }
 int InstrEmit_fcmpo(PPCHIRBuilder& f, const InstrData& i) {