OPCODE_INSERT
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@ -4782,16 +4782,22 @@ EMITTER_OPCODE_TABLE(
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// ============================================================================
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// ============================================================================
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// OPCODE_INSERT
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// OPCODE_INSERT
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// ============================================================================
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// ============================================================================
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EMITTER(INSERT_I8, MATCH(I<OPCODE_INSERT, V128<>, V128<>, I64<>, I8<>>)) {
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EMITTER(INSERT_I8, MATCH(I<OPCODE_INSERT, V128<>, V128<>, I8<>, I8<>>)) {
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static void Emit(X64Emitter& e, const EmitArgType& i) {
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static void Emit(X64Emitter& e, const EmitArgType& i) {
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assert_true(i.src2.is_constant);
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e.vpinsrb(i.dest, i.src3.reg().cvt32(), i.src2.constant() ^ 0x3);
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}
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}
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};
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};
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EMITTER(INSERT_I16, MATCH(I<OPCODE_INSERT, V128<>, V128<>, I64<>, I16<>>)) {
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EMITTER(INSERT_I16, MATCH(I<OPCODE_INSERT, V128<>, V128<>, I8<>, I16<>>)) {
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static void Emit(X64Emitter& e, const EmitArgType& i) {
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static void Emit(X64Emitter& e, const EmitArgType& i) {
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assert_true(i.src2.is_constant);
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e.vpinsrw(i.dest, i.src3.reg().cvt32(), i.src2.constant() ^ 0x1);
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}
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}
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};
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};
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EMITTER(INSERT_I32, MATCH(I<OPCODE_INSERT, V128<>, V128<>, I64<>, I32<>>)) {
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EMITTER(INSERT_I32, MATCH(I<OPCODE_INSERT, V128<>, V128<>, I8<>, I32<>>)) {
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static void Emit(X64Emitter& e, const EmitArgType& i) {
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static void Emit(X64Emitter& e, const EmitArgType& i) {
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assert_true(i.src2.is_constant);
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e.vpinsrd(i.dest, i.src3, i.src2.constant());
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}
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}
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};
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};
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EMITTER_OPCODE_TABLE(
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EMITTER_OPCODE_TABLE(
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@ -1809,9 +1809,12 @@ Value* HIRBuilder::CountLeadingZeros(Value* value) {
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Value* HIRBuilder::Insert(Value* value, Value* index, Value* part) {
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Value* HIRBuilder::Insert(Value* value, Value* index, Value* part) {
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// TODO(benvanik): could do some of this as constants.
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// TODO(benvanik): could do some of this as constants.
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Value* trunc_index =
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index->type != INT8_TYPE ? Truncate(index, INT8_TYPE) : index;
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Instr* i = AppendInstr(OPCODE_INSERT_info, 0, AllocValue(value->type));
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Instr* i = AppendInstr(OPCODE_INSERT_info, 0, AllocValue(value->type));
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i->set_src1(value);
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i->set_src1(value);
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i->set_src2(ZeroExtend(index, INT64_TYPE));
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i->set_src2(trunc_index);
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i->set_src3(part);
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i->set_src3(part);
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return i->dest;
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return i->dest;
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}
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}
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@ -18,66 +18,69 @@ using namespace alloy::test;
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using alloy::frontend::ppc::PPCContext;
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using alloy::frontend::ppc::PPCContext;
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TEST_CASE("INSERT_INT8", "[instr]") {
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TEST_CASE("INSERT_INT8", "[instr]") {
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TestFunction test([](hir::HIRBuilder& b) {
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StoreVR(b, 3, b.Insert(LoadVR(b, 4), LoadGPR(b, 4),
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b.Truncate(LoadGPR(b, 5), INT8_TYPE)));
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b.Return();
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});
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for (int i = 0; i < 16; ++i) {
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for (int i = 0; i < 16; ++i) {
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test.Run([i](PPCContext* ctx) {
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TestFunction test([i](hir::HIRBuilder& b) {
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ctx->v[4] = vec128b(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13,
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StoreVR(b, 3, b.Insert(LoadVR(b, 4), b.LoadConstant(i),
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14, 15);
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b.Truncate(LoadGPR(b, 5), INT8_TYPE)));
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ctx->r[4] = i;
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b.Return();
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ctx->r[5] = 100 + i;
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});
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},
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test.Run(
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[i](PPCContext* ctx) {
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[i](PPCContext* ctx) {
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auto result = ctx->v[3];
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ctx->v[4] =
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auto expected = vec128b(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12,
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vec128b(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
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13, 14, 15);
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ctx->r[4] = i;
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expected.i8[i ^ 0x3] = 100 + i;
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ctx->r[5] = 100 + i;
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REQUIRE(result == expected);
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},
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});
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[i](PPCContext* ctx) {
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auto result = ctx->v[3];
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auto expected =
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vec128b(0, 1, 2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15);
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expected.i8[i ^ 0x3] = 100 + i;
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REQUIRE(result == expected);
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});
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}
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}
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}
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}
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TEST_CASE("INSERT_INT16", "[instr]") {
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TEST_CASE("INSERT_INT16", "[instr]") {
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TestFunction test([](hir::HIRBuilder& b) {
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StoreVR(b, 3, b.Insert(LoadVR(b, 4), LoadGPR(b, 4),
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b.Truncate(LoadGPR(b, 5), INT16_TYPE)));
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b.Return();
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});
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for (int i = 0; i < 8; ++i) {
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for (int i = 0; i < 8; ++i) {
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test.Run([i](PPCContext* ctx) {
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TestFunction test([i](hir::HIRBuilder& b) {
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ctx->v[4] = vec128s(0, 1, 2, 3, 4, 5, 6, 7);
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StoreVR(b, 3, b.Insert(LoadVR(b, 4), b.LoadConstant(i),
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ctx->r[4] = i;
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b.Truncate(LoadGPR(b, 5), INT16_TYPE)));
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ctx->r[5] = 100 + i;
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b.Return();
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},
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});
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[i](PPCContext* ctx) {
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test.Run(
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auto result = ctx->v[3];
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[i](PPCContext* ctx) {
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auto expected = vec128s(0, 1, 2, 3, 4, 5, 6, 7);
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ctx->v[4] = vec128s(0, 1, 2, 3, 4, 5, 6, 7);
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expected.i16[i ^ 0x1] = 100 + i;
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ctx->r[4] = i;
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REQUIRE(result == expected);
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ctx->r[5] = 100 + i;
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});
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},
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[i](PPCContext* ctx) {
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auto result = ctx->v[3];
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auto expected = vec128s(0, 1, 2, 3, 4, 5, 6, 7);
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expected.i16[i ^ 0x1] = 100 + i;
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REQUIRE(result == expected);
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});
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}
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}
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}
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}
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TEST_CASE("INSERT_INT32", "[instr]") {
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TEST_CASE("INSERT_INT32", "[instr]") {
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TestFunction test([](hir::HIRBuilder& b) {
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StoreVR(b, 3, b.Insert(LoadVR(b, 4), LoadGPR(b, 4),
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b.Truncate(LoadGPR(b, 5), INT32_TYPE)));
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b.Return();
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});
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for (int i = 0; i < 4; ++i) {
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for (int i = 0; i < 4; ++i) {
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test.Run([i](PPCContext* ctx) {
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TestFunction test([i](hir::HIRBuilder& b) {
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ctx->v[4] = vec128i(0, 1, 2, 3);
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StoreVR(b, 3, b.Insert(LoadVR(b, 4), b.LoadConstant(i),
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ctx->r[4] = i;
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b.Truncate(LoadGPR(b, 5), INT32_TYPE)));
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ctx->r[5] = 100 + i;
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b.Return();
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},
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});
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[i](PPCContext* ctx) {
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test.Run(
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auto result = ctx->v[3];
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[i](PPCContext* ctx) {
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auto expected = vec128i(0, 1, 2, 3);
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ctx->v[4] = vec128i(0, 1, 2, 3);
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expected.i32[i] = 100 + i;
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ctx->r[4] = i;
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REQUIRE(result == expected);
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ctx->r[5] = 100 + i;
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});
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},
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[i](PPCContext* ctx) {
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auto result = ctx->v[3];
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auto expected = vec128i(0, 1, 2, 3);
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expected.i32[i] = 100 + i;
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REQUIRE(result == expected);
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});
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}
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}
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}
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}
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