diff --git a/src/xenia/app/xenia_main.cc b/src/xenia/app/xenia_main.cc index d90246936..25fba3735 100644 --- a/src/xenia/app/xenia_main.cc +++ b/src/xenia/app/xenia_main.cc @@ -95,9 +95,15 @@ UPDATE_from_bool(mount_cache, 2024, 8, 31, 20, false); DEFINE_transient_path(target, "", "Specifies the target .xex or .iso to execute.", "General"); +#ifndef XE_PLATFORM_WIN32 +DEFINE_transient_bool(portable, false, + "Specifies if Xenia should run in portable mode.", + "General"); +#else DEFINE_transient_bool(portable, true, "Specifies if Xenia should run in portable mode.", "General"); +#endif DECLARE_bool(debug); @@ -421,7 +427,7 @@ bool EmulatorApp::OnInitialize() { if (!cvars::portable && !std::filesystem::exists(storage_root / "portable.txt")) { storage_root = xe::filesystem::GetUserFolder(); -#if defined(XE_PLATFORM_WIN32) || defined(XE_PLATFORM_GNU_LINUX) +#if defined(XE_PLATFORM_WIN32) || defined(XE_PLATFORM_LINUX) storage_root = storage_root / "Xenia"; #else // TODO(Triang3l): Point to the app's external storage "files" directory diff --git a/src/xenia/gpu/pm4_command_processor_implement.h b/src/xenia/gpu/pm4_command_processor_implement.h index 3cb6fbb91..5b04df510 100644 --- a/src/xenia/gpu/pm4_command_processor_implement.h +++ b/src/xenia/gpu/pm4_command_processor_implement.h @@ -902,7 +902,8 @@ bool COMMAND_PROCESSOR::ExecutePacketType3_EVENT_WRITE_SHD( data_value = GpuSwap(data_value, endianness); uint8_t* write_destination = memory_->TranslatePhysical(address); if (address > 0x1FFFFFFF) { - uint32_t writeback_base = register_file_->values[XE_GPU_REG_WRITEBACK_BASE]; + uint32_t writeback_base = + register_file_->values[XE_GPU_REG_WRITEBACK_START]; uint32_t writeback_size = register_file_->values[XE_GPU_REG_WRITEBACK_SIZE]; uint32_t writeback_offset = address - writeback_base; // check whether the guest has written writeback base. if they haven't, skip diff --git a/src/xenia/gpu/register_table.inc b/src/xenia/gpu/register_table.inc index 125c635fb..328247872 100644 --- a/src/xenia/gpu/register_table.inc +++ b/src/xenia/gpu/register_table.inc @@ -2,7 +2,7 @@ ****************************************************************************** * Xenia : Xbox 360 Emulator Research Project * ****************************************************************************** - * Copyright 2013 Ben Vanik. All rights reserved. * + * Copyright 2025 Ben Vanik. All rights reserved. * * Released under the BSD license - see LICENSE in the root for more details. * ****************************************************************************** */ @@ -11,24 +11,152 @@ // constructing various tables. // Almost all of these values are taken directly from: -// https://github.com/freedreno/amd-gpu/blob/master/include/reg/yamato/22/yamato_offset.h +// https://github.com/xenon-emu/xenon/blob/main/Xenon/Core/XGPU/XenosRegisters.h // #define XE_GPU_REGISTER(index, type, name) +XE_GPU_REGISTER(0x0000, kDword, RBBM_RTL_RELEASE) +XE_GPU_REGISTER(0x0001, kDword, RBBM_PATCH_RELEASE) +XE_GPU_REGISTER(0x0002, kDword, RBBM_AUXILIARY_CONFIG) +XE_GPU_REGISTER(0x0004, kDword, BIOS_0_SCRATCH) +XE_GPU_REGISTER(0x0005, kDword, BIOS_1_SCRATCH) +XE_GPU_REGISTER(0x0006, kDword, BIOS_2_SCRATCH) +XE_GPU_REGISTER(0x0007, kDword, BIOS_3_SCRATCH) +XE_GPU_REGISTER(0x0008, kDword, BIOS_4_SCRATCH) +XE_GPU_REGISTER(0x0009, kDword, BIOS_5_SCRATCH) +XE_GPU_REGISTER(0x000A, kDword, BIOS_6_SCRATCH) +XE_GPU_REGISTER(0x000B, kDword, BIOS_7_SCRATCH) +XE_GPU_REGISTER(0x0038, kDword, CONFIG_CNTL) +XE_GPU_REGISTER(0x0039, kDword, CONFIG_XSTRAP) +XE_GPU_REGISTER(0x003A, kDword, CONFIG_XSTRAP2) +XE_GPU_REGISTER(0x003B, kDword, RBBM_CNTL) +XE_GPU_REGISTER(0x003C, kDword, RBBM_SOFT_RESET) +XE_GPU_REGISTER(0x003D, kDword, RBBM_SKEW_CNTL) +XE_GPU_REGISTER(0x0040, kDword, MH_MMU_CONFIG) +XE_GPU_REGISTER(0x0041, kDword, MH_MMU_VA_RANGE) +XE_GPU_REGISTER(0x0042, kDword, MH_MMU_PT_BASE) +XE_GPU_REGISTER(0x0043, kDword, MH_MMU_PAGE_FAULT) +XE_GPU_REGISTER(0x0044, kDword, MH_MMU_TRAN_ERROR) +XE_GPU_REGISTER(0x0045, kDword, MH_MMU_INVALIDATE) +XE_GPU_REGISTER(0x0046, kDword, MH_MMU_MPU_BASE) +XE_GPU_REGISTER(0x0047, kDword, MH_MMU_MPU_END) XE_GPU_REGISTER(0x0048, kDword, BIF_PERFCOUNTER0_SELECT) XE_GPU_REGISTER(0x0049, kDword, BIF_PERFCOUNTER0_HI) XE_GPU_REGISTER(0x004A, kDword, BIF_PERFCOUNTER0_LOW) -XE_GPU_REGISTER(0x1C5, kDword, CP_RB_WPTR) - -XE_GPU_REGISTER(0x01DD, kDword, SCRATCH_ADDR) +XE_GPU_REGISTER(0x0064, kDword, ROM_PAR_DATA_REG) +XE_GPU_REGISTER(0x0065, kDword, ROM_BAD_PIPE_DISABLE_REGISTER) +XE_GPU_REGISTER(0x0066, kDword, ROM_PAR_ADDR_REG) +XE_GPU_REGISTER(0x0067, kDword, ROM_CLK_REG) +XE_GPU_REGISTER(0x0068, kDword, ROM_BAD_PIPE_FUSE_REG) +XE_GPU_REGISTER(0x0069, kDword, DBG_CNTL1_REG) +XE_GPU_REGISTER(0x006A, kDword, ROM_SIMD_PIPE_DISABLE_REGISTER) +XE_GPU_REGISTER(0x006B, kDword, DBG_READ_REG) +XE_GPU_REGISTER(0x006C, kDword, ROM_PADS_REG) +XE_GPU_REGISTER(0x006D, kDword, SOFT_STRAP_CNTL) +XE_GPU_REGISTER(0x006E, kDword, CONFIG_XSTRAP3) +XE_GPU_REGISTER(0x006F, kDword, EXTERN_TRIG_CNTL) +XE_GPU_REGISTER(0x0070, kDword, ROM_STATUS_REG) +XE_GPU_REGISTER(0x0071, kDword, ROM_PORT_REG) +XE_GPU_REGISTER(0x0080, kDword, SCLK_PWRMGT_CNTL1_REG) +XE_GPU_REGISTER(0x0081, kDword, SCLK_PWRMGT_CNTL2_REG) +XE_GPU_REGISTER(0x0082, kDword, SCLK_PWRMGT_CNTL3_REG) +XE_GPU_REGISTER(0x0083, kDword, FSB_STOP_CLK_REG) +XE_GPU_REGISTER(0x0084, kDword, SPLL_CNTL_REG) +XE_GPU_REGISTER(0x0085, kDword, CG_SCRATCH1) +XE_GPU_REGISTER(0x0086, kDword, RCLK_PWRMGT_CNTL_REG) +XE_GPU_REGISTER(0x0087, kDword, PSRO_REG) +XE_GPU_REGISTER(0x0091, kDword, RPLL_CNTL_REG) +XE_GPU_REGISTER(0x0092, kDword, FPLL_CNTL_REG) +XE_GPU_REGISTER(0x0093, kDword, CG_INT_MASK_REG) +XE_GPU_REGISTER(0x0094, kDword, CG_INT_STAT_REG) +XE_GPU_REGISTER(0x0095, kDword, CG_INT_ACK_REG) +XE_GPU_REGISTER(0x00A0, kDword, MCLK_CNTL1_REG) +XE_GPU_REGISTER(0x00A1, kDword, MPLL_CNTL_REG) +XE_GPU_REGISTER(0x00A2, kDword, YCLK_CNTL1_REG) +XE_GPU_REGISTER(0x00A3, kDword, MDLL_CNTL1_REG) +XE_GPU_REGISTER(0x00A6, kDword, MCLK_PWRMGT_CNTL_REG) +XE_GPU_REGISTER(0x00A7, kDword, MCLK_TEST_CNTL1_REG) +XE_GPU_REGISTER(0x00A8, kDword, CGM_MC0_IO_CNTL) +XE_GPU_REGISTER(0x00A9, kDword, CGM_DRAM_CNTL_REG) +XE_GPU_REGISTER(0x00AA, kDword, CGM_MC1_IO_CNTL) +XE_GPU_REGISTER(0x0128, kDword, PCLK_SOFT_RESET) +XE_GPU_REGISTER(0x0129, kDword, DCCG_SCLK_R_DISP_CNTL) +XE_GPU_REGISTER(0x012F, kDword, SCLK_G_SCL1_CNTL) +XE_GPU_REGISTER(0x0132, kDword, SCLK_SOFT_RESET) +XE_GPU_REGISTER(0x0133, kDword, DCCG_CLK_CNTL) +XE_GPU_REGISTER(0x0135, kDword, TEST_COUNT_CNTL) +XE_GPU_REGISTER(0x0136, kDword, DCCG_TEST_CLK_SEL) +XE_GPU_REGISTER(0x013C, kDword, DVOACLK_CNTL) +XE_GPU_REGISTER(0x0140, kDword, DCCG_ONE_SHOT_CLOCKING_CNTL) +XE_GPU_REGISTER(0x0141, kDword, DCCG_ONE_SHOT_STOP_CLOCKS_CNTL) +XE_GPU_REGISTER(0x0142, kDword, DCCG_ONE_SHOT_RUN_CLOCKS_CNTL) +XE_GPU_REGISTER(0x0143, kDword, DCCG_ONE_SHOT_RUN_CLOCKS_COUNT) +XE_GPU_REGISTER(0x0144, kDword, DCCG_DEBUG) +XE_GPU_REGISTER(0x015C, kDword, SCLK_G_DCP_CNTL) +XE_GPU_REGISTER(0x01C0, kDword, CP_RB_BASE) +XE_GPU_REGISTER(0x01C1, kDword, CP_RB_CNTL) +XE_GPU_REGISTER(0x01C3, kDword, CP_RB_RPTR_ADDR) +XE_GPU_REGISTER(0x01C4, kDword, CP_RB_RPTR) +XE_GPU_REGISTER(0x01C5, kDword, CP_RB_WPTR) +XE_GPU_REGISTER(0x01C6, kDword, CP_RB_WPTR_DELAY) +XE_GPU_REGISTER(0x01C7, kDword, CP_RB_RPTR_WR) +XE_GPU_REGISTER(0x01C8, kDword, CP_DMA_SRC_ADDR) +XE_GPU_REGISTER(0x01C9, kDword, CP_DMA_DST_ADDR) +XE_GPU_REGISTER(0x01CA, kDword, CP_DMA_COMMAND) +XE_GPU_REGISTER(0x01CC, kDword, CP_IB1_BASE) +XE_GPU_REGISTER(0x01CD, kDword, CP_IB1_BUFSZ) +XE_GPU_REGISTER(0x01CE, kDword, CP_IB2_BASE) +XE_GPU_REGISTER(0x01CF, kDword, CP_IB2_BUFSZ) +XE_GPU_REGISTER(0x01D0, kDword, CP_RT_BASE) +XE_GPU_REGISTER(0x01D1, kDword, CP_RT_BUFSZ) +XE_GPU_REGISTER(0x01D2, kDword, CP_RT_ST_BASE) +XE_GPU_REGISTER(0x01D3, kDword, CP_RT_ST_BUFSZ) +XE_GPU_REGISTER(0x01D5, kDword, CP_QUEUE_THRESHOLDS) +XE_GPU_REGISTER(0x01D6, kDword, CP_MEQ_THRESHOLDS) +XE_GPU_REGISTER(0x01D7, kDword, CP_CSQ_AVAIL) +XE_GPU_REGISTER(0x01D8, kDword, CP_STQ_AVAIL) +XE_GPU_REGISTER(0x01D9, kDword, CP_MEQ_AVAIL) +XE_GPU_REGISTER(0x01DA, kDword, CP_CMD_INDEX) +XE_GPU_REGISTER(0x01DB, kDword, CP_CMD_DATA) XE_GPU_REGISTER(0x01DC, kDword, SCRATCH_UMSK) -XE_GPU_REGISTER(0x01E6, kDword, CP_PERFCOUNTER0_SELECT) -XE_GPU_REGISTER(0x01E7, kDword, CP_PERFCOUNTER0_LOW) -XE_GPU_REGISTER(0x01E8, kDword, CP_PERFCOUNTER0_HI) +XE_GPU_REGISTER(0x01DD, kDword, SCRATCH_ADDR) +XE_GPU_REGISTER(0x01DE, kDword, SCRATCH_CMP_HI) +XE_GPU_REGISTER(0x01DF, kDword, SCRATCH_CMP_LO) +XE_GPU_REGISTER(0x01E0, kDword, CP_DMA_TABLE_ADDR) +XE_GPU_REGISTER(0x01E1, kDword, CP_DMA_SRC_ADDR_STAT) +XE_GPU_REGISTER(0x01E2, kDword, CP_DMA_DST_ADDR_STAT) +XE_GPU_REGISTER(0x01E3, kDword, CP_DMA_COMMAND_STAT) +XE_GPU_REGISTER(0x01E4, kDword, CP_DMA_STAT) +XE_GPU_REGISTER(0x01E5, kDword, CP_DMA_ACT_DSCR_STAT) +XE_GPU_REGISTER(0x01E6, kDword, CP_PERFCOUNTER_SELECT) +XE_GPU_REGISTER(0x01E7, kDword, CP_PERFCOUNTER_LO) +XE_GPU_REGISTER(0x01E8, kDword, CP_PERFCOUNTER_HI) +XE_GPU_REGISTER(0x01E9, kDword, SCRATCH_CMP_CNTL) +XE_GPU_REGISTER(0x01EA, kDword, CP_ME_RDADDR) +XE_GPU_REGISTER(0x01EC, kDword, CP_STATE_DEBUG_INDEX) +XE_GPU_REGISTER(0x01ED, kDword, CP_STATE_DEBUG_DATA) +XE_GPU_REGISTER(0x01EE, kDword, CP_NV_FLAGS_0) +XE_GPU_REGISTER(0x01EF, kDword, CP_NV_FLAGS_1) +XE_GPU_REGISTER(0x01F0, kDword, CP_NV_FLAGS_2) +XE_GPU_REGISTER(0x01F1, kDword, CP_NV_FLAGS_3) +XE_GPU_REGISTER(0x01F2, kDword, CP_INT_CNTL) +XE_GPU_REGISTER(0x01F3, kDword, CP_INT_STATUS) +XE_GPU_REGISTER(0x01F4, kDword, CP_INT_ACK) XE_GPU_REGISTER(0x01F5, kDword, CP_PERFMON_CNTL) +XE_GPU_REGISTER(0x01F6, kDword, CP_ME_CNTL) +XE_GPU_REGISTER(0x01F7, kDword, CP_ME_STATUS) +XE_GPU_REGISTER(0x01F8, kDword, CP_ME_RAM_WADDR) +XE_GPU_REGISTER(0x01F9, kDword, CP_ME_RAM_RADDR) +XE_GPU_REGISTER(0x01FA, kDword, CP_ME_RAM_DATA) +XE_GPU_REGISTER(0x01FB, kDword, CP_SNOOP_CNTL) +XE_GPU_REGISTER(0x01FC, kDword, CP_DEBUG) +XE_GPU_REGISTER(0x01FD, kDword, CP_CSQ_RB_STAT) +XE_GPU_REGISTER(0x01FE, kDword, CP_CSQ_IB1_STAT) +XE_GPU_REGISTER(0x01FF, kDword, CP_CSQ_IB2_STAT) +XE_GPU_REGISTER(0x0394, kDword, NQWAIT_UNTIL) XE_GPU_REGISTER(0x0395, kDword, RBBM_PERFCOUNTER0_SELECT) XE_GPU_REGISTER(0x0396, kDword, RBBM_PERFCOUNTER1_SELECT) XE_GPU_REGISTER(0x0397, kDword, RBBM_PERFCOUNTER0_LOW) @@ -36,23 +164,172 @@ XE_GPU_REGISTER(0x0398, kDword, RBBM_PERFCOUNTER0_HI) XE_GPU_REGISTER(0x0399, kDword, RBBM_PERFCOUNTER1_LOW) XE_GPU_REGISTER(0x039A, kDword, RBBM_PERFCOUNTER1_HI) -// XAM reads this directly and stores it to a struct, have not tracked where it -// goes from there PM4 command PM4_MEM_WRITE_CNTR is supposed to write this to -// memory XE_GPU_REGISTER(0x44b, kDword,CP_PROG_COUNTER ) -XE_GPU_REGISTER(0x045E, kDword, CALLBACK_ACK) - -XE_GPU_REGISTER(0x0578, kDword, SCRATCH_REG0) // interrupt sync -XE_GPU_REGISTER(0x0579, kDword, SCRATCH_REG1) // present interval +XE_GPU_REGISTER(0x039B, kDword, RBBM_DEBUG) +XE_GPU_REGISTER(0x039C, kDword, RBBM_STATUS2) +XE_GPU_REGISTER(0x039D, kDword, RBBM_CRC32) +XE_GPU_REGISTER(0x03A0, kDword, RBBM_DEBUG_OUT) +XE_GPU_REGISTER(0x03A1, kDword, RBBM_DEBUG_CNTL) +XE_GPU_REGISTER(0x03B2, kDword, RBBM_WAIT_IDLE_CLOCKS) +XE_GPU_REGISTER(0x03B3, kDword, RBBM_READ_ERROR) +XE_GPU_REGISTER(0x03B4, kDword, RBBM_INT_CNTL) +XE_GPU_REGISTER(0x03B5, kDword, RBBM_INT_STATUS) +XE_GPU_REGISTER(0x03B6, kDword, RBBM_INT_ACK) +XE_GPU_REGISTER(0x03B7, kDword, MASTER_INT_SIGNAL) +XE_GPU_REGISTER(0x03F9, kDword, RBBM_PERIPHID1) +XE_GPU_REGISTER(0x03FA, kDword, RBBM_PERIPHID2) +XE_GPU_REGISTER(0x0440, kDword, CP_NON_PREFETCH_CNTRS) +XE_GPU_REGISTER(0x0442, kDword, CP_STQ_RT_STAT) +XE_GPU_REGISTER(0x0443, kDword, CP_STQ_ST_STAT) +XE_GPU_REGISTER(0x0444, kDword, CP_STQ_RT_ST_STAT) +XE_GPU_REGISTER(0x0445, kDword, CP_RT_DMA_SRC_ADDR) +XE_GPU_REGISTER(0x0446, kDword, CP_RT_DMA_DST_ADDR) +XE_GPU_REGISTER(0x0447, kDword, CP_RT_DMA_COMMAND) +XE_GPU_REGISTER(0x0448, kDword, CP_RT_ME_RAM_WADDR) +XE_GPU_REGISTER(0x0449, kDword, CP_RT_ME_RAM_RADDR) +XE_GPU_REGISTER(0x044A, kDword, CP_RT_ME_RAM_DATA) +XE_GPU_REGISTER(0x044B, kDword, CP_PROG_COUNTER) +XE_GPU_REGISTER(0x044C, kDword, CP_RT_ME_RDADDR) +XE_GPU_REGISTER(0x044D, kDword, CP_ST_BASE) +XE_GPU_REGISTER(0x044E, kDword, CP_ST_BUFSZ) +XE_GPU_REGISTER(0x044F, kDword, CP_MEQ_STAT) +XE_GPU_REGISTER(0x0452, kDword, CP_MIU_TAG_STAT0) +XE_GPU_REGISTER(0x0453, kDword, CP_MIU_TAG_STAT1) +XE_GPU_REGISTER(0x0454, kDword, CP_BIN_MASK_LO) +XE_GPU_REGISTER(0x0455, kDword, CP_BIN_MASK_HI) +XE_GPU_REGISTER(0x0456, kDword, CP_BIN_SELECT_LO) +XE_GPU_REGISTER(0x0457, kDword, CP_BIN_SELECT_HI) +XE_GPU_REGISTER(0x0458, kDword, CP_RT_BIN_MASK_LO) +XE_GPU_REGISTER(0x0459, kDword, CP_RT_BIN_MASK_HI) +XE_GPU_REGISTER(0x045A, kDword, CP_RT_BIN_SELECT_LO) +XE_GPU_REGISTER(0x045B, kDword, CP_RT_BIN_SELECT_HI) +XE_GPU_REGISTER(0x045C, kDword, CP_CPU_INT_CNTL) +XE_GPU_REGISTER(0x045D, kDword, CP_CPU_INT_STATUS) +XE_GPU_REGISTER(0x045E, kDword, CP_CPU_INT_ACK) +XE_GPU_REGISTER(0x045F, kDword, CP_PFP_UCODE_ADDR) +XE_GPU_REGISTER(0x0460, kDword, CP_PFP_UCODE_DATA) +XE_GPU_REGISTER(0x0461, kDword, CP_PFP_RT_UCODE_ADDR) +XE_GPU_REGISTER(0x0462, kDword, CP_PFP_RT_UCODE_DATA) +XE_GPU_REGISTER(0x047E, kDword, CP_RT_STAT) +XE_GPU_REGISTER(0x047F, kDword, CP_STAT) +XE_GPU_REGISTER(0x04C0, kDword, CP_RT0_COMMAND) +XE_GPU_REGISTER(0x04C1, kDword, CP_RT0_POLL_ADDRESS) +XE_GPU_REGISTER(0x04C2, kDword, CP_RT0_REFERENCE) +XE_GPU_REGISTER(0x04C3, kDword, CP_RT0_MASK) +XE_GPU_REGISTER(0x04C4, kDword, CP_RT0_BADR) +XE_GPU_REGISTER(0x04C5, kDword, CP_RT0_SIZE) +XE_GPU_REGISTER(0x04C6, kDword, CP_RT1_COMMAND) +XE_GPU_REGISTER(0x04C7, kDword, CP_RT1_POLL_ADDRESS) +XE_GPU_REGISTER(0x04C8, kDword, CP_RT1_REFERENCE) +XE_GPU_REGISTER(0x04C9, kDword, CP_RT1_MASK) +XE_GPU_REGISTER(0x04CA, kDword, CP_RT1_BADR) +XE_GPU_REGISTER(0x04CB, kDword, CP_RT1_SIZE) +XE_GPU_REGISTER(0x04CC, kDword, CP_RT2_COMMAND) +XE_GPU_REGISTER(0x04CD, kDword, CP_RT2_POLL_ADDRESS) +XE_GPU_REGISTER(0x04CE, kDword, CP_RT2_REFERENCE) +XE_GPU_REGISTER(0x04CF, kDword, CP_RT2_MASK) +XE_GPU_REGISTER(0x04D0, kDword, CP_RT2_BADR) +XE_GPU_REGISTER(0x04D1, kDword, CP_RT2_SIZE) +XE_GPU_REGISTER(0x04D2, kDword, CP_RT3_COMMAND) +XE_GPU_REGISTER(0x04D3, kDword, CP_RT3_POLL_ADDRESS) +XE_GPU_REGISTER(0x04D4, kDword, CP_RT3_REFERENCE) +XE_GPU_REGISTER(0x04D5, kDword, CP_RT3_MASK) +XE_GPU_REGISTER(0x04D6, kDword, CP_RT3_BADR) +XE_GPU_REGISTER(0x04D7, kDword, CP_RT3_SIZE) +XE_GPU_REGISTER(0x04D8, kDword, CP_RT4_COMMAND) +XE_GPU_REGISTER(0x04D9, kDword, CP_RT4_POLL_ADDRESS) +XE_GPU_REGISTER(0x04DA, kDword, CP_RT4_REFERENCE) +XE_GPU_REGISTER(0x04DB, kDword, CP_RT4_MASK) +XE_GPU_REGISTER(0x04DC, kDword, CP_RT4_BADR) +XE_GPU_REGISTER(0x04DD, kDword, CP_RT4_SIZE) +XE_GPU_REGISTER(0x04DE, kDword, CP_RT5_COMMAND) +XE_GPU_REGISTER(0x04DF, kDword, CP_RT5_POLL_ADDRESS) +XE_GPU_REGISTER(0x04E0, kDword, CP_RT5_REFERENCE) +XE_GPU_REGISTER(0x04E1, kDword, CP_RT5_MASK) +XE_GPU_REGISTER(0x04E2, kDword, CP_RT5_BADR) +XE_GPU_REGISTER(0x04E3, kDword, CP_RT5_SIZE) +XE_GPU_REGISTER(0x04E4, kDword, CP_RT6_COMMAND) +XE_GPU_REGISTER(0x04E5, kDword, CP_RT6_POLL_ADDRESS) +XE_GPU_REGISTER(0x04E6, kDword, CP_RT6_REFERENCE) +XE_GPU_REGISTER(0x04E7, kDword, CP_RT6_MASK) +XE_GPU_REGISTER(0x04E8, kDword, CP_RT6_BADR) +XE_GPU_REGISTER(0x04E9, kDword, CP_RT6_SIZE) +XE_GPU_REGISTER(0x04EA, kDword, CP_RT7_COMMAND) +XE_GPU_REGISTER(0x04EB, kDword, CP_RT7_POLL_ADDRESS) +XE_GPU_REGISTER(0x04EC, kDword, CP_RT7_REFERENCE) +XE_GPU_REGISTER(0x04ED, kDword, CP_RT7_MASK) +XE_GPU_REGISTER(0x04EE, kDword, CP_RT7_BADR) +XE_GPU_REGISTER(0x04EF, kDword, CP_RT7_SIZE) +XE_GPU_REGISTER(0x04F0, kDword, CP_RT8_COMMAND) +XE_GPU_REGISTER(0x04F1, kDword, CP_RT8_POLL_ADDRESS) +XE_GPU_REGISTER(0x04F2, kDword, CP_RT8_REFERENCE) +XE_GPU_REGISTER(0x04F3, kDword, CP_RT8_MASK) +XE_GPU_REGISTER(0x04F4, kDword, CP_RT8_BADR) +XE_GPU_REGISTER(0x04F5, kDword, CP_RT8_SIZE) +XE_GPU_REGISTER(0x04F6, kDword, CP_RT9_COMMAND) +XE_GPU_REGISTER(0x04F7, kDword, CP_RT9_POLL_ADDRESS) +XE_GPU_REGISTER(0x04F8, kDword, CP_RT9_REFERENCE) +XE_GPU_REGISTER(0x04F9, kDword, CP_RT9_MASK) +XE_GPU_REGISTER(0x04FA, kDword, CP_RT9_BADR) +XE_GPU_REGISTER(0x04FB, kDword, CP_RT9_SIZE) +XE_GPU_REGISTER(0x04FC, kDword, CP_RT10_COMMAND) +XE_GPU_REGISTER(0x04FD, kDword, CP_RT10_POLL_ADDRESS) +XE_GPU_REGISTER(0x04FE, kDword, CP_RT10_REFERENCE) +XE_GPU_REGISTER(0x04FF, kDword, CP_RT10_MASK) +XE_GPU_REGISTER(0x0500, kDword, CP_RT10_BADR) +XE_GPU_REGISTER(0x0501, kDword, CP_RT10_SIZE) +XE_GPU_REGISTER(0x0502, kDword, CP_RT11_COMMAND) +XE_GPU_REGISTER(0x0503, kDword, CP_RT11_POLL_ADDRESS) +XE_GPU_REGISTER(0x0504, kDword, CP_RT11_REFERENCE) +XE_GPU_REGISTER(0x0505, kDword, CP_RT11_MASK) +XE_GPU_REGISTER(0x0506, kDword, CP_RT11_BADR) +XE_GPU_REGISTER(0x0507, kDword, CP_RT11_SIZE) +XE_GPU_REGISTER(0x0508, kDword, CP_RT12_COMMAND) +XE_GPU_REGISTER(0x0509, kDword, CP_RT12_POLL_ADDRESS) +XE_GPU_REGISTER(0x050A, kDword, CP_RT12_REFERENCE) +XE_GPU_REGISTER(0x050B, kDword, CP_RT12_MASK) +XE_GPU_REGISTER(0x050C, kDword, CP_RT12_BADR) +XE_GPU_REGISTER(0x050D, kDword, CP_RT12_SIZE) +XE_GPU_REGISTER(0x050E, kDword, CP_RT13_COMMAND) +XE_GPU_REGISTER(0x050F, kDword, CP_RT13_POLL_ADDRESS) +XE_GPU_REGISTER(0x0510, kDword, CP_RT13_REFERENCE) +XE_GPU_REGISTER(0x0511, kDword, CP_RT13_MASK) +XE_GPU_REGISTER(0x0512, kDword, CP_RT13_BADR) +XE_GPU_REGISTER(0x0513, kDword, CP_RT13_SIZE) +XE_GPU_REGISTER(0x0514, kDword, CP_RT14_COMMAND) +XE_GPU_REGISTER(0x0515, kDword, CP_RT14_POLL_ADDRESS) +XE_GPU_REGISTER(0x0516, kDword, CP_RT14_REFERENCE) +XE_GPU_REGISTER(0x0517, kDword, CP_RT14_MASK) +XE_GPU_REGISTER(0x0518, kDword, CP_RT14_RADR) +XE_GPU_REGISTER(0x0519, kDword, CP_RT14_SIZE) +XE_GPU_REGISTER(0x051A, kDword, CP_RT15_COMMAND) +XE_GPU_REGISTER(0x051B, kDword, CP_RT15_POLL_ADDRESS) +XE_GPU_REGISTER(0x051C, kDword, CP_RT15_REFERENCE) +XE_GPU_REGISTER(0x051D, kDword, CP_RT15_MASK) +XE_GPU_REGISTER(0x051E, kDword, CP_RT15_BADR) +XE_GPU_REGISTER(0x051F, kDword, CP_RT15_SIZE) +XE_GPU_REGISTER(0x0520, kDword, CP_RT_POLL_INTERVAL) +XE_GPU_REGISTER(0x0521, kDword, CP_VIP_EOL_EOF_COUNTER) +XE_GPU_REGISTER(0x0522, kDword, CP_D1_EOL_SOF_COUNTER) +XE_GPU_REGISTER(0x0523, kDword, CP_D2_EOL_SOF_COUNTER) +XE_GPU_REGISTER(0x0578, kDword, SCRATCH_REG0) +XE_GPU_REGISTER(0x0579, kDword, SCRATCH_REG1) XE_GPU_REGISTER(0x057A, kDword, SCRATCH_REG2) XE_GPU_REGISTER(0x057B, kDword, SCRATCH_REG3) -XE_GPU_REGISTER(0x057C, kDword, - SCRATCH_REG4) // originally this was named CALLBACK_ADDRESS, - // but that didnt make sense +XE_GPU_REGISTER(0x057C, kDword, SCRATCH_REG4) XE_GPU_REGISTER(0x057D, kDword, SCRATCH_REG5) XE_GPU_REGISTER(0x057E, kDword, SCRATCH_REG6) XE_GPU_REGISTER(0x057F, kDword, SCRATCH_REG7) +XE_GPU_REGISTER(0x0580, kDword, BIOS_8_SCRATCH) +XE_GPU_REGISTER(0x0581, kDword, BIOS_9_SCRATCH) +XE_GPU_REGISTER(0x0582, kDword, BIOS_10_SCRATCH) +XE_GPU_REGISTER(0x0583, kDword, BIOS_11_SCRATCH) +XE_GPU_REGISTER(0x0584, kDword, BIOS_12_SCRATCH) +XE_GPU_REGISTER(0x0585, kDword, BIOS_13_SCRATCH) +XE_GPU_REGISTER(0x0586, kDword, BIOS_14_SCRATCH) +XE_GPU_REGISTER(0x0587, kDword, BIOS_15_SCRATCH) XE_GPU_REGISTER(0x05C8, kDword, WAIT_UNTIL) +XE_GPU_REGISTER(0x05C9, kDword, RBBM_ISYNC_CNTL) // src is flash_xam.xex, i've seen it used by the kernel and aurora // seems to have a negative value while the gpu is busy @@ -66,38 +343,227 @@ XE_GPU_REGISTER(0x05C8, kDword, WAIT_UNTIL) // low 2 bits encode two different fields? // xboxkrnl just does addr |2 when assigning // XE_GPU_REGISTER(0x70C, kDword, CP_RB_RPTR_ADDR) -XE_GPU_REGISTER(0x0815, kDword, MC0_PERFCOUNTER0_SELECT) + +XE_GPU_REGISTER(0x05F0, kDword, CP_IB2D_BASE) +XE_GPU_REGISTER(0x05F1, kDword, CP_IB2D_BUFSZ) +XE_GPU_REGISTER(0x05F2, kDword, CP_DEFAULT_PITCH_OFFSET) +XE_GPU_REGISTER(0x05F3, kDword, CP_DEFAULT2_PITCH_OFFSET) +XE_GPU_REGISTER(0x05F4, kDword, CP_DEFAULT_SC_BOTTOM_RIGHT) +XE_GPU_REGISTER(0x05F5, kDword, CP_DEFAULT2_SC_BOTTOM_RIGHT) +XE_GPU_REGISTER(0x05F6, kDword, CP_2D_BRUSH_BASE) +XE_GPU_REGISTER(0x05F7, kDword, CP_2D_PALETTE_BASE) +XE_GPU_REGISTER(0x05F8, kDword, CP_2D_IMMD_BASE) +XE_GPU_REGISTER(0x05F9, kDword, CP_2D_BOOLEANS) +XE_GPU_REGISTER(0x0600, kDword, CP_ME_VS_EVENT_SRC) +XE_GPU_REGISTER(0x0601, kDword, CP_ME_VS_EVENT_ADDR) +XE_GPU_REGISTER(0x0602, kDword, CP_ME_VS_EVENT_DATA) +XE_GPU_REGISTER(0x0603, kDword, CP_ME_VS_EVENT_ADDR_SWM) +XE_GPU_REGISTER(0x0604, kDword, CP_ME_VS_EVENT_DATA_SWM) +XE_GPU_REGISTER(0x0605, kDword, CP_ME_PS_EVENT_SRC) +XE_GPU_REGISTER(0x0606, kDword, CP_ME_PS_EVENT_ADDR) +XE_GPU_REGISTER(0x0607, kDword, CP_ME_PS_EVENT_DATA) +XE_GPU_REGISTER(0x0608, kDword, CP_ME_PS_EVENT_ADDR_SWM) +XE_GPU_REGISTER(0x0609, kDword, CP_ME_PS_EVENT_DATA_SWM) +XE_GPU_REGISTER(0x060A, kDword, CP_ME_CF_EVENT_SRC) +XE_GPU_REGISTER(0x060B, kDword, CP_ME_CF_EVENT_ADDR) +XE_GPU_REGISTER(0x060C, kDword, CP_ME_CF_EVENT_DATA) +XE_GPU_REGISTER(0x060D, kDword, CP_ME_NRT_ADDR) +XE_GPU_REGISTER(0x060E, kDword, CP_ME_NRT_DATA) +XE_GPU_REGISTER(0x060F, kDword, CP_ME_RT_ADDR) +XE_GPU_REGISTER(0x0610, kDword, CP_ME_RT_DATA) +XE_GPU_REGISTER(0x0611, kDword, CP_ME_SCREEN_EXT_RPT_ADDR) +XE_GPU_REGISTER(0x0612, kDword, CP_ME_VS_FETCH_DONE_SRC) +XE_GPU_REGISTER(0x0613, kDword, CP_ME_VS_FETCH_DONE_ADDR) +XE_GPU_REGISTER(0x0614, kDword, CP_ME_VS_FETCH_DONE_DATA) +XE_GPU_REGISTER(0x0800, kDword, MC0_CNTL) +XE_GPU_REGISTER(0x0801, kDword, MC0_DRAM_CONFIG) +XE_GPU_REGISTER(0x0802, kDword, MC0_BSB_SNOOPED_TIMER_CNTL) +XE_GPU_REGISTER(0x0803, kDword, MC0_TUNING_0) +XE_GPU_REGISTER(0x0804, kDword, MC0_TUNING_1) +XE_GPU_REGISTER(0x0805, kDword, MC0_RD_BUFFER_CNTL_0) +XE_GPU_REGISTER(0x0806, kDword, MC0_ARBITRATION_CNTL) +XE_GPU_REGISTER(0x0807, kDword, MC0_TIMING_CNTL_0) +XE_GPU_REGISTER(0x0808, kDword, MC0_TIMING_CNTL_1) +XE_GPU_REGISTER(0x0809, kDword, MC0_TIMING_CNTL_2) +XE_GPU_REGISTER(0x080A, kDword, MC0_PAD_CAL_CNTL) +XE_GPU_REGISTER(0x080B, kDword, MC0_DRAM_CMD) +XE_GPU_REGISTER(0x080C, kDword, MC0_DRAM_DATA) +XE_GPU_REGISTER(0x080D, kDword, MC0_POINTER) +XE_GPU_REGISTER(0x080E, kDword, MC0_RDBUF_DATA) +XE_GPU_REGISTER(0x080F, kDword, MC0_DRAM_DQ) +XE_GPU_REGISTER(0x0810, kDword, MC0_STATUS_0) +XE_GPU_REGISTER(0x0811, kDword, MC0_STATUS_1) +XE_GPU_REGISTER(0x0812, kDword, MC0_CRC_CNTL) +XE_GPU_REGISTER(0x0813, kDword, MC0_DEBUG) +XE_GPU_REGISTER(0x0814, kDword, MC0_CRC_READ) +XE_GPU_REGISTER(0x0815, kDword, MC0_PERFCOUNTER0_CNTL) XE_GPU_REGISTER(0x0816, kDword, MC0_PERFCOUNTER0_HI) XE_GPU_REGISTER(0x0817, kDword, MC0_PERFCOUNTER0_LOW) -XE_GPU_REGISTER(0x0855, kDword, MC1_PERFCOUNTER0_SELECT) +XE_GPU_REGISTER(0x0818, kDword, MC0_PERFCOUNTER1_CNTL) +XE_GPU_REGISTER(0x0819, kDword, MC0_PERFCOUNTER1_HI) +XE_GPU_REGISTER(0x081A, kDword, MC0_PERFCOUNTER1_LOW) +XE_GPU_REGISTER(0x081B, kDword, MC0_INTERRUPT_MASK) +XE_GPU_REGISTER(0x081C, kDword, MC0_INTERRUPT_STATUS) +XE_GPU_REGISTER(0x081D, kDword, MC0_INTERRUPT_ACK) +XE_GPU_REGISTER(0x081E, kDword, MC0_SECURE_MEMORY_APERTURE_LOG_MH) +XE_GPU_REGISTER(0x081F, kDword, MC0_SECURE_MEMORY_APERTURE_LOG_BIU) +XE_GPU_REGISTER(0x0820, kDword, MC0_WR_STR_DLL_0) +XE_GPU_REGISTER(0x0821, kDword, MC0_WR_STR_DLL_1) +XE_GPU_REGISTER(0x0822, kDword, MC0_DLL_MASTER_ADJ_0) +XE_GPU_REGISTER(0x0823, kDword, MC0_DLL_MASTER_ADJ_1) +XE_GPU_REGISTER(0x0824, kDword, MC0_TERM_CNTL) +XE_GPU_REGISTER(0x0825, kDword, MC0_WR_DATA_DLY_0) +XE_GPU_REGISTER(0x0826, kDword, MC0_WR_DATA_DLY_1) +XE_GPU_REGISTER(0x0827, kDword, MC0_RD_STR_DLY_0) +XE_GPU_REGISTER(0x0828, kDword, MC0_RD_STR_DLY_1) +XE_GPU_REGISTER(0x0829, kDword, MC0_WR_STR_DLY) +XE_GPU_REGISTER(0x082A, kDword, MC0_PAD_CAL_STATUS) +XE_GPU_REGISTER(0x082B, kDword, MC0_RD_STR_DLY_CNTL) +XE_GPU_REGISTER(0x0830, kDword, MC0_PAD_IF_CNTL) +XE_GPU_REGISTER(0x0831, kDword, MC0_PAD_IF_CNTL_2) +XE_GPU_REGISTER(0x0832, kDword, MC0_RD_BUFFER_CNTL_1) +XE_GPU_REGISTER(0x0840, kDword, MC1_CNTL) +XE_GPU_REGISTER(0x0841, kDword, MC1_DRAM_CONFIG) +XE_GPU_REGISTER(0x0842, kDword, MC1_BSB_SNOOPED_TIMER_CNTL) +XE_GPU_REGISTER(0x0843, kDword, MC1_TUNING_0) +XE_GPU_REGISTER(0x0844, kDword, MC1_TUNING_1) +XE_GPU_REGISTER(0x0845, kDword, MC1_RD_BUFFER_CNTL_0) +XE_GPU_REGISTER(0x0846, kDword, MC1_ARBITRATION_CNTL) +XE_GPU_REGISTER(0x0847, kDword, MC1_TIMING_CNTL_0) +XE_GPU_REGISTER(0x0848, kDword, MC1_TIMING_CNTL_1) +XE_GPU_REGISTER(0x0849, kDword, MC1_TIMING_CNTL_2) +XE_GPU_REGISTER(0x084A, kDword, MC1_PAD_CAL_CNTL) +XE_GPU_REGISTER(0x084B, kDword, MC1_DRAM_CMD) +XE_GPU_REGISTER(0x084C, kDword, MC1_DRAM_DATA) +XE_GPU_REGISTER(0x084D, kDword, MC1_POINTER) +XE_GPU_REGISTER(0x084E, kDword, MC1_RDBUF_DATA) +XE_GPU_REGISTER(0x084F, kDword, MC1_DRAM_DQ) +XE_GPU_REGISTER(0x0850, kDword, MC1_STATUS_0) +XE_GPU_REGISTER(0x0851, kDword, MC1_STATUS_1) +XE_GPU_REGISTER(0x0852, kDword, MC1_CRC_CNTL) +XE_GPU_REGISTER(0x0853, kDword, MC1_DEBUG) +XE_GPU_REGISTER(0x0854, kDword, MC1_CRC_READ) +XE_GPU_REGISTER(0x0855, kDword, MC1_PERFCOUNTER0_CNTL) XE_GPU_REGISTER(0x0856, kDword, MC1_PERFCOUNTER0_HI) XE_GPU_REGISTER(0x0857, kDword, MC1_PERFCOUNTER0_LOW) -// base GPU virtual address of the xps region. Most guests write 0xC0100000 here -XE_GPU_REGISTER(0x0A02, kDword, XPS_BASE) -// will usually be set higher, but is effectively 0x700000 bytes long -XE_GPU_REGISTER(0x0A03, kDword, XPS_SIZE) -// usually 0xC0000000 -XE_GPU_REGISTER(0x0A04, kDword, WRITEBACK_BASE) -// usually 0x0100000 +XE_GPU_REGISTER(0x0858, kDword, MC1_PERFCOUNTER1_CNTL) +XE_GPU_REGISTER(0x0859, kDword, MC1_PERFCOUNTER1_HI) +XE_GPU_REGISTER(0x085A, kDword, MC1_PERFCOUNTER1_LOW) +XE_GPU_REGISTER(0x085B, kDword, MC1_INTERRUPT_MASK) +XE_GPU_REGISTER(0x085C, kDword, MC1_INTERRUPT_STATUS) +XE_GPU_REGISTER(0x085D, kDword, MC1_INTERRUPT_ACK) +XE_GPU_REGISTER(0x085E, kDword, MC1_SECURE_MEMORY_APERTURE_LOG_MH) +XE_GPU_REGISTER(0x085F, kDword, MC1_SECURE_MEMORY_APERTURE_LOG_BIU) +XE_GPU_REGISTER(0x0860, kDword, MC1_WR_STR_DLL_0) +XE_GPU_REGISTER(0x0861, kDword, MC1_WR_STR_DLL_1) +XE_GPU_REGISTER(0x0862, kDword, MC1_DLL_MASTER_ADJ_0) +XE_GPU_REGISTER(0x0863, kDword, MC1_DLL_MASTER_ADJ_1) +XE_GPU_REGISTER(0x0864, kDword, MC1_TERM_CNTL) +XE_GPU_REGISTER(0x0865, kDword, MC1_WR_DATA_DLY_0) +XE_GPU_REGISTER(0x0866, kDword, MC1_WR_DATA_DLY_1) +XE_GPU_REGISTER(0x0867, kDword, MC1_RD_STR_DLY_0) +XE_GPU_REGISTER(0x0868, kDword, MC1_RD_STR_DLY_1) +XE_GPU_REGISTER(0x0869, kDword, MC1_WR_STR_DLY) +XE_GPU_REGISTER(0x086A, kDword, MC1_PAD_CAL_STATUS) +XE_GPU_REGISTER(0x086B, kDword, MC1_RD_STR_DLY_CNTL) +XE_GPU_REGISTER(0x0870, kDword, MC1_PAD_IF_CNTL) +XE_GPU_REGISTER(0x0871, kDword, MC1_PAD_IF_CNTL_2) +XE_GPU_REGISTER(0x0872, kDword, MC1_RD_BUFFER_CNTL_1) +XE_GPU_REGISTER(0x0A00, kDword, FB_START) +XE_GPU_REGISTER(0x0A01, kDword, FB_SIZE) +XE_GPU_REGISTER(0x0A02, kDword, PG_START) +XE_GPU_REGISTER(0x0A03, kDword, PG_SIZE) +XE_GPU_REGISTER(0x0A04, kDword, WRITEBACK_START) XE_GPU_REGISTER(0x0A05, kDword, WRITEBACK_SIZE) - -XE_GPU_REGISTER(0x0A18, kDword, MH_PERFCOUNTER0_SELECT) -XE_GPU_REGISTER(0x0A19, kDword, MH_PERFCOUNTER0_HI) -XE_GPU_REGISTER(0x0A1A, kDword, MH_PERFCOUNTER0_LOW) -XE_GPU_REGISTER(0x0A1B, kDword, MH_PERFCOUNTER1_SELECT) -XE_GPU_REGISTER(0x0A1C, kDword, MH_PERFCOUNTER1_HI) -XE_GPU_REGISTER(0x0A1D, kDword, MH_PERFCOUNTER1_LOW) -XE_GPU_REGISTER(0x0A1E, kDword, MH_PERFCOUNTER2_SELECT) -XE_GPU_REGISTER(0x0A1F, kDword, MH_PERFCOUNTER2_HI) -XE_GPU_REGISTER(0x0A20, kDword, MH_PERFCOUNTER2_LOW) - +XE_GPU_REGISTER(0x0A06, kDword, MH_CNTL) +XE_GPU_REGISTER(0x0A07, kDword, MH_STATUS) +XE_GPU_REGISTER(0x0A08, kDword, MH_INT_MASK) +XE_GPU_REGISTER(0x0A09, kDword, MH_INT_STATUS) +XE_GPU_REGISTER(0x0A0A, kDword, MH_INT_CLEAR) +XE_GPU_REGISTER(0x0A0B, kDword, MH_INT_SIGNAL) +XE_GPU_REGISTER(0x0A0C, kDword, PGL_CTL0) +XE_GPU_REGISTER(0x0A0D, kDword, PGL_CTL1) +XE_GPU_REGISTER(0x0A10, kDword, DC_SURFACE_0_BASE) +XE_GPU_REGISTER(0x0A11, kDword, DC_SURFACE_0_EXTENT) +XE_GPU_REGISTER(0x0A12, kDword, DC_SURFACE_0_INFO) +XE_GPU_REGISTER(0x0A13, kDword, DC_SURFACE_2_BASE) +XE_GPU_REGISTER(0x0A14, kDword, DC_SURFACE_2_EXTENT) +XE_GPU_REGISTER(0x0A15, kDword, DC_SURFACE_2_INFO) +XE_GPU_REGISTER(0x0A18, kDword, MH_PERFMON_PERFCOUNTER0_SELECT) +XE_GPU_REGISTER(0x0A19, kDword, MH_PERFMON_PERFCOUNTER0_HI) +XE_GPU_REGISTER(0x0A1A, kDword, MH_PERFMON_PERFCOUNTER0_LOW) +XE_GPU_REGISTER(0x0A1B, kDword, MH_PERFMON_PERFCOUNTER1_SELECT) +XE_GPU_REGISTER(0x0A1C, kDword, MH_PERFMON_PERFCOUNTER1_HI) +XE_GPU_REGISTER(0x0A1D, kDword, MH_PERFMON_PERFCOUNTER1_LOW) +XE_GPU_REGISTER(0x0A1E, kDword, MH_PERFMON_PERFCOUNTER2_SELECT) +XE_GPU_REGISTER(0x0A1F, kDword, MH_PERFMON_PERFCOUNTER2_HI) +XE_GPU_REGISTER(0x0A20, kDword, MH_PERFMON_PERFCOUNTER2_LOW) +XE_GPU_REGISTER(0x0A21, kDword, DC_SURFACE_1_BASE) +XE_GPU_REGISTER(0x0A22, kDword, DC_SURFACE_1_EXTENT) +XE_GPU_REGISTER(0x0A23, kDword, DC_SURFACE_1_INFO) +XE_GPU_REGISTER(0x0A29, kDword, COHER_SIZE_PM4) +XE_GPU_REGISTER(0x0A2A, kDword, COHER_BASE_PM4) +XE_GPU_REGISTER(0x0A2B, kDword, COHER_STATUS_PM4) +XE_GPU_REGISTER(0x0A2C, kDword, COHER_SIZE_RT) +XE_GPU_REGISTER(0x0A2D, kDword, COHER_BASE_RT) +XE_GPU_REGISTER(0x0A2E, kDword, COHER_STATUS_RT) XE_GPU_REGISTER(0x0A2F, kDword, COHER_SIZE_HOST) XE_GPU_REGISTER(0x0A30, kDword, COHER_BASE_HOST) XE_GPU_REGISTER(0x0A31, kDword, COHER_STATUS_HOST) // Status flags of viz queries, doesn't seem to be read back by d3d // queries 0x00 to 0x1f (be), bit set when visible +XE_GPU_REGISTER(0x0A40, kDword, MH_ARBITER_CONFIG) +XE_GPU_REGISTER(0x0BFE, kDword, MH_DEBUG_INDEX) +XE_GPU_REGISTER(0x0BFF, kDword, MH_DEBUG_DATA) +XE_GPU_REGISTER(0x0C00, kDword, RTS_INITIATOR) +XE_GPU_REGISTER(0x0C01, kDword, RTS_BOUNDBOX_START) +XE_GPU_REGISTER(0x0C02, kDword, RTS_BOUNDBOX_END) +XE_GPU_REGISTER(0x0C03, kDword, RTS_BARYC_REF_VTX_X) +XE_GPU_REGISTER(0x0C04, kDword, RTS_BARYC_REF_VTX_Y) +XE_GPU_REGISTER(0x0C05, kDword, RTS_I_W_DX) +XE_GPU_REGISTER(0x0C06, kDword, RTS_J_W_DY) +XE_GPU_REGISTER(0x0C07, kDword, RTS_INV_W_REF) +XE_GPU_REGISTER(0x0C08, kDword, RTS_INV_W_DX) +XE_GPU_REGISTER(0x0C09, kDword, RTS_INV_W_DY) +XE_GPU_REGISTER(0x0C0A, kDword, RTS_I_W_REF) +XE_GPU_REGISTER(0x0C0B, kDword, RTS_I_W_DY) +XE_GPU_REGISTER(0x0C0C, kDword, RTS_J_W_REF) +XE_GPU_REGISTER(0x0C0D, kDword, RTS_J_W_DX) +XE_GPU_REGISTER(0x0C0E, kDword, RTS_Z_REF) +XE_GPU_REGISTER(0x0C0F, kDword, RTS_Z_DX_MSBS) +XE_GPU_REGISTER(0x0C10, kDword, RTS_Z_DY_MSBS) +XE_GPU_REGISTER(0x0C11, kDword, RTS_Z_DX_DY_LSBS) +XE_GPU_REGISTER(0x0C12, kDword, RTS_Z_MIN) +XE_GPU_REGISTER(0x0C13, kDword, RTS_Z_MAX) +XE_GPU_REGISTER(0x0C14, kDword, RTS_EDGE_0_DIST_LSBS) +XE_GPU_REGISTER(0x0C15, kDword, RTS_EDGE_1_DIST_LSBS) +XE_GPU_REGISTER(0x0C16, kDword, RTS_EDGE_2_DIST_LSBS) +XE_GPU_REGISTER(0x0C17, kDword, RTS_EDGE_DIST_MSBS) +XE_GPU_REGISTER(0x0C18, kDword, RTS_WD_EDGE_0_DIST_LSBS) +XE_GPU_REGISTER(0x0C19, kDword, RTS_WD_EDGE_1_DIST_LSBS) +XE_GPU_REGISTER(0x0C1A, kDword, RTS_WD_EDGE_2_DIST_LSBS) +XE_GPU_REGISTER(0x0C1B, kDword, RTS_WD_EDGE_DIST_MSBS) +XE_GPU_REGISTER(0x0C1C, kDword, RTS_EDGE_0_DX) +XE_GPU_REGISTER(0x0C1D, kDword, RTS_EDGE_0_DY) +XE_GPU_REGISTER(0x0C1E, kDword, RTS_EDGE_1_DX) +XE_GPU_REGISTER(0x0C1F, kDword, RTS_EDGE_1_DY) +XE_GPU_REGISTER(0x0C20, kDword, RTS_EDGE_2_DX) +XE_GPU_REGISTER(0x0C21, kDword, RTS_EDGE_2_DY) +XE_GPU_REGISTER(0x0C22, kDword, RTS_MISC) +XE_GPU_REGISTER(0x0C2C, kDword, VGT_VTX_VECT_EJECT_REG) +XE_GPU_REGISTER(0x0C2D, kDword, VGT_DMA_DATA_FIFO_DEPTH) +XE_GPU_REGISTER(0x0C2E, kDword, VGT_DMA_REQ_FIFO_DEPTH) +XE_GPU_REGISTER(0x0C2F, kDword, VGT_DRAW_INIT_FIFO_DEPTH) +XE_GPU_REGISTER(0x0C30, kDword, VGT_LAST_COPY_STATE) +XE_GPU_REGISTER(0x0C38, kDword, VGT_DEBUG_CNTL) +XE_GPU_REGISTER(0x0C39, kDword, VGT_DEBUG_DATA) +XE_GPU_REGISTER(0x0C3A, kDword, VGT_CRC_SQ_DATA) +XE_GPU_REGISTER(0x0C3B, kDword, VGT_CRC_SQ_CTRL) +XE_GPU_REGISTER(0x0C3C, kDword, VGT_CNTL_STATUS) +XE_GPU_REGISTER(0x0C40, kDword, PA_SC_LINE_STIPPLE_STATE) +XE_GPU_REGISTER(0x0C41, kDword, PA_SC_MULTI_CHIP_CNTL) XE_GPU_REGISTER(0x0C44, kDword, PA_SC_VIZ_QUERY_STATUS_0) // queries 0x20 to 0x3f (be) XE_GPU_REGISTER(0x0C45, kDword, PA_SC_VIZ_QUERY_STATUS_1) @@ -115,8 +581,14 @@ XE_GPU_REGISTER(0x0C51, kDword, VGT_PERFCOUNTER2_HI) XE_GPU_REGISTER(0x0C52, kDword, VGT_PERFCOUNTER3_LOW) XE_GPU_REGISTER(0x0C53, kDword, VGT_PERFCOUNTER3_HI) +XE_GPU_REGISTER(0x0C80, kDword, PA_SU_DEBUG_CNTL) +XE_GPU_REGISTER(0x0C81, kDword, PA_SU_DEBUG_DATA) +XE_GPU_REGISTER(0x0C82, kDword, PA_SC_DEBUG_CNTL) +XE_GPU_REGISTER(0x0C83, kDword, PA_SC_DEBUG_DATA) +XE_GPU_REGISTER(0x0C84, kDword, PA_CL_CNTL_STATUS) XE_GPU_REGISTER(0x0C85, kDword, PA_CL_ENHANCE) +XE_GPU_REGISTER(0x0C86, kDword, PA_SU_FACE_DATA) XE_GPU_REGISTER(0x0C88, kDword, PA_SU_PERFCOUNTER0_SELECT) XE_GPU_REGISTER(0x0C89, kDword, PA_SU_PERFCOUNTER1_SELECT) XE_GPU_REGISTER(0x0C8A, kDword, PA_SU_PERFCOUNTER2_SELECT) @@ -129,6 +601,7 @@ XE_GPU_REGISTER(0x0C90, kDword, PA_SU_PERFCOUNTER2_LOW) XE_GPU_REGISTER(0x0C91, kDword, PA_SU_PERFCOUNTER2_HI) XE_GPU_REGISTER(0x0C92, kDword, PA_SU_PERFCOUNTER3_LOW) XE_GPU_REGISTER(0x0C93, kDword, PA_SU_PERFCOUNTER3_HI) +XE_GPU_REGISTER(0x0C94, kDword, PA_SU_CNTL_STATUS) XE_GPU_REGISTER(0x0C98, kDword, PA_SC_PERFCOUNTER0_SELECT) XE_GPU_REGISTER(0x0C99, kDword, PA_SC_PERFCOUNTER1_SELECT) XE_GPU_REGISTER(0x0C9A, kDword, PA_SC_PERFCOUNTER2_SELECT) @@ -142,12 +615,43 @@ XE_GPU_REGISTER(0x0CA1, kDword, PA_SC_PERFCOUNTER2_HI) XE_GPU_REGISTER(0x0CA2, kDword, PA_SC_PERFCOUNTER3_LOW) XE_GPU_REGISTER(0x0CA3, kDword, PA_SC_PERFCOUNTER3_HI) +XE_GPU_REGISTER(0x0CA4, kDword, PA_SC_CNTL_STATUS) +XE_GPU_REGISTER(0x0CA5, kDword, PA_SC_ENHANCE) +XE_GPU_REGISTER(0x0CC0, kDword, PA_SC_FIFO_SIZE) XE_GPU_REGISTER(0x0D00, kDword, SQ_GPR_MANAGEMENT) -XE_GPU_REGISTER(0x0D01, kDword, SQ_FLOW_CONTROL) -XE_GPU_REGISTER(0x0D02, kDword, SQ_INST_STORE_MANAGMENT) - +XE_GPU_REGISTER(0x0D01, kDword, SQ_FLOW_CNTL) +XE_GPU_REGISTER(0x0D02, kDword, SQ_INST_STORE_MANAGEMENT) +XE_GPU_REGISTER(0x0D03, kDword, SQ_RESOURCE_MANAGMENT) XE_GPU_REGISTER(0x0D04, kDword, SQ_EO_RT) +XE_GPU_REGISTER(0x0D05, kDword, SQ_DEBUG_MISC) +XE_GPU_REGISTER(0x0D06, kDword, SQ_ACTIVITY_METER_CNTL) +XE_GPU_REGISTER(0x0D07, kDword, SQ_ACTIVITY_METER_STATUS) +XE_GPU_REGISTER(0x0D08, kDword, SQ_INPUT_ARB_PRIORITY) +XE_GPU_REGISTER(0x0D09, kDword, SQ_THREAD_ARB_PRIORITY) +XE_GPU_REGISTER(0x0D34, kDword, SQ_INT_CNTL) +XE_GPU_REGISTER(0x0D35, kDword, SQ_INT_STATUS) +XE_GPU_REGISTER(0x0D36, kDword, SQ_INT_ACK) +XE_GPU_REGISTER(0x0DAE, kDword, SQ_DEBUG_INPUT_FSM) +XE_GPU_REGISTER(0x0DAF, kDword, SQ_DEBUG_CONST_MGR_FSM) +XE_GPU_REGISTER(0x0DB0, kDword, SQ_DEBUG_TP_FSM) +XE_GPU_REGISTER(0x0DB1, kDword, SQ_DEBUG_FSM_ALU_0) +XE_GPU_REGISTER(0x0DB2, kDword, SQ_DEBUG_FSM_ALU_1) +XE_GPU_REGISTER(0x0DB3, kDword, SQ_DEBUG_EXP_ALLOC) +XE_GPU_REGISTER(0x0DB4, kDword, SQ_DEBUG_PTR_BUFF) +XE_GPU_REGISTER(0x0DB5, kDword, SQ_DEBUG_GPR_VTX) +XE_GPU_REGISTER(0x0DB6, kDword, SQ_DEBUG_GPR_PIX) +XE_GPU_REGISTER(0x0DB7, kDword, SQ_DEBUG_TB_STATUS_SEL) +XE_GPU_REGISTER(0x0DB8, kDword, SQ_DEBUG_VTX_TB_0) +XE_GPU_REGISTER(0x0DB9, kDword, SQ_DEBUG_VTX_TB_1) +XE_GPU_REGISTER(0x0DBA, kDword, SQ_DEBUG_VTX_TB_STATUS_REG) +XE_GPU_REGISTER(0x0DBB, kDword, SQ_DEBUG_VTX_TB_STATE_MEM) +XE_GPU_REGISTER(0x0DBC, kDword, SQ_DEBUG_PIX_TB_0) +XE_GPU_REGISTER(0x0DBD, kDword, SQ_DEBUG_PIX_TB_STATUS_REG_0) +XE_GPU_REGISTER(0x0DBE, kDword, SQ_DEBUG_PIX_TB_STATUS_REG_1) +XE_GPU_REGISTER(0x0DBF, kDword, SQ_DEBUG_PIX_TB_STATUS_REG_2) +XE_GPU_REGISTER(0x0DC0, kDword, SQ_DEBUG_PIX_TB_STATUS_REG_3) +XE_GPU_REGISTER(0x0DC1, kDword, SQ_DEBUG_PIX_TB_STATE_MEM) XE_GPU_REGISTER(0x0DC8, kDword, SQ_PERFCOUNTER0_SELECT) XE_GPU_REGISTER(0x0DC9, kDword, SQ_PERFCOUNTER1_SELECT) XE_GPU_REGISTER(0x0DCA, kDword, SQ_PERFCOUNTER2_SELECT) @@ -161,12 +665,25 @@ XE_GPU_REGISTER(0x0DD1, kDword, SQ_PERFCOUNTER2_HI) XE_GPU_REGISTER(0x0DD2, kDword, SQ_PERFCOUNTER3_LOW) XE_GPU_REGISTER(0x0DD3, kDword, SQ_PERFCOUNTER3_HI) XE_GPU_REGISTER(0x0DD4, kDword, SX_PERFCOUNTER0_SELECT) +XE_GPU_REGISTER(0x0DD5, kDword, SX_PERFCOUNTER1_SELECT) +XE_GPU_REGISTER(0x0DD6, kDword, SX_PERFCOUNTER2_SELECT) +XE_GPU_REGISTER(0x0DD7, kDword, SX_PERFCOUNTER3_SELECT) XE_GPU_REGISTER(0x0DD8, kDword, SX_PERFCOUNTER0_LOW) XE_GPU_REGISTER(0x0DD9, kDword, SX_PERFCOUNTER0_HI) // Set with WAIT_UNTIL = WAIT_3D_IDLECLEAN +XE_GPU_REGISTER(0x0DDA, kDword, SX_PERFCOUNTER1_LOW) +XE_GPU_REGISTER(0x0DDB, kDword, SX_PERFCOUNTER1_HI) +XE_GPU_REGISTER(0x0DDC, kDword, SX_PERFCOUNTER2_LOW) +XE_GPU_REGISTER(0x0DDD, kDword, SX_PERFCOUNTER2_HI) +XE_GPU_REGISTER(0x0DDE, kDword, SX_PERFCOUNTER3_LOW) +XE_GPU_REGISTER(0x0DDF, kDword, SX_PERFCOUNTER3_HI) XE_GPU_REGISTER(0x0E00, kDword, TC_CNTL_STATUS) +XE_GPU_REGISTER(0x0E01, kDword, TP_DEBUG0) +XE_GPU_REGISTER(0x0E02, kDword, TCR_CHICKEN) +XE_GPU_REGISTER(0x0E03, kDword, TCF_CHICKEN) +XE_GPU_REGISTER(0x0E04, kDword, TCM_CHICKEN) XE_GPU_REGISTER(0x0E05, kDword, TCR_PERFCOUNTER0_SELECT) XE_GPU_REGISTER(0x0E06, kDword, TCR_PERFCOUNTER0_HI) XE_GPU_REGISTER(0x0E07, kDword, TCR_PERFCOUNTER0_LOW) @@ -174,6 +691,14 @@ XE_GPU_REGISTER(0x0E08, kDword, TCR_PERFCOUNTER1_SELECT) XE_GPU_REGISTER(0x0E09, kDword, TCR_PERFCOUNTER1_HI) XE_GPU_REGISTER(0x0E0A, kDword, TCR_PERFCOUNTER1_LOW) +XE_GPU_REGISTER(0x0E17, kDword, TP_TC_CLKGATE_CNTL) +XE_GPU_REGISTER(0x0E18, kDword, TPC_CNTL_STATUS) +XE_GPU_REGISTER(0x0E19, kDword, TPC_DEBUG0) +XE_GPU_REGISTER(0x0E1A, kDword, TPC_DEBUG1) +XE_GPU_REGISTER(0x0E1B, kDword, TPC_CHICKEN) +XE_GPU_REGISTER(0x0E1C, kDword, TP0_CNTL_STATUS) +XE_GPU_REGISTER(0x0E1D, kDword, TP0_DEBUG) +XE_GPU_REGISTER(0x0E1E, kDword, TP0_CHICKEN) XE_GPU_REGISTER(0x0E1F, kDword, TP0_PERFCOUNTER0_SELECT) XE_GPU_REGISTER(0x0E20, kDword, TP0_PERFCOUNTER0_HI) XE_GPU_REGISTER(0x0E21, kDword, TP0_PERFCOUNTER0_LOW) @@ -181,6 +706,9 @@ XE_GPU_REGISTER(0x0E22, kDword, TP0_PERFCOUNTER1_SELECT) XE_GPU_REGISTER(0x0E23, kDword, TP0_PERFCOUNTER1_HI) XE_GPU_REGISTER(0x0E24, kDword, TP0_PERFCOUNTER1_LOW) +XE_GPU_REGISTER(0x0E25, kDword, TP1_CNTL_STATUS) +XE_GPU_REGISTER(0x0E26, kDword, TP1_DEBUG) +XE_GPU_REGISTER(0x0E27, kDword, TP1_CHICKEN) XE_GPU_REGISTER(0x0E28, kDword, TP1_PERFCOUNTER0_SELECT) XE_GPU_REGISTER(0x0E29, kDword, TP1_PERFCOUNTER0_HI) XE_GPU_REGISTER(0x0E2A, kDword, TP1_PERFCOUNTER0_LOW) @@ -188,6 +716,9 @@ XE_GPU_REGISTER(0x0E2B, kDword, TP1_PERFCOUNTER1_SELECT) XE_GPU_REGISTER(0x0E2C, kDword, TP1_PERFCOUNTER1_HI) XE_GPU_REGISTER(0x0E2D, kDword, TP1_PERFCOUNTER1_LOW) +XE_GPU_REGISTER(0x0E2E, kDword, TP2_CNTL_STATUS) +XE_GPU_REGISTER(0x0E2F, kDword, TP2_DEBUG) +XE_GPU_REGISTER(0x0E30, kDword, TP2_CHICKEN) XE_GPU_REGISTER(0x0E31, kDword, TP2_PERFCOUNTER0_SELECT) XE_GPU_REGISTER(0x0E32, kDword, TP2_PERFCOUNTER0_HI) XE_GPU_REGISTER(0x0E33, kDword, TP2_PERFCOUNTER0_LOW) @@ -195,19 +726,21 @@ XE_GPU_REGISTER(0x0E34, kDword, TP2_PERFCOUNTER1_SELECT) XE_GPU_REGISTER(0x0E35, kDword, TP2_PERFCOUNTER1_HI) XE_GPU_REGISTER(0x0E36, kDword, TP2_PERFCOUNTER1_LOW) +XE_GPU_REGISTER(0x0E37, kDword, TP3_CNTL_STATUS) +XE_GPU_REGISTER(0x0E38, kDword, TP3_DEBUG) +XE_GPU_REGISTER(0x0E39, kDword, TP3_CHICKEN) XE_GPU_REGISTER(0x0E3A, kDword, TP3_PERFCOUNTER0_SELECT) XE_GPU_REGISTER(0x0E3B, kDword, TP3_PERFCOUNTER0_HI) XE_GPU_REGISTER(0x0E3C, kDword, TP3_PERFCOUNTER0_LOW) XE_GPU_REGISTER(0x0E3D, kDword, TP3_PERFCOUNTER1_SELECT) XE_GPU_REGISTER(0x0E3E, kDword, TP3_PERFCOUNTER1_HI) XE_GPU_REGISTER(0x0E3F, kDword, TP3_PERFCOUNTER1_LOW) - -// Set with WAIT_UNTIL = WAIT_3D_IDLECLEAN -XE_GPU_REGISTER(0x0E40, kDword, UNKNOWN_0E40) - -// Set during GPU initialization by D3D -XE_GPU_REGISTER(0x0E42, kDword, UNKNOWN_0E42) - +XE_GPU_REGISTER(0x0E40, kDword, VC_CNTL) +XE_GPU_REGISTER(0x0E41, kDword, VC_CNTL_STATUS) +XE_GPU_REGISTER(0x0E42, kDword, VC_FIFO_DEPTHS) +XE_GPU_REGISTER(0x0E43, kDword, VC_DEBUG_CNTL) +XE_GPU_REGISTER(0x0E44, kDword, VC_DEBUG_DATA) +XE_GPU_REGISTER(0x0E45, kDword, VC_ENHANCE) XE_GPU_REGISTER(0x0E48, kDword, VC_PERFCOUNTER0_SELECT) XE_GPU_REGISTER(0x0E49, kDword, VC_PERFCOUNTER0_HI) XE_GPU_REGISTER(0x0E4A, kDword, VC_PERFCOUNTER0_LOW) @@ -280,24 +813,79 @@ XE_GPU_REGISTER(0x0F0C, kDword, BC_PERFCOUNTER2_LOW) XE_GPU_REGISTER(0x0F0D, kDword, BC_PERFCOUNTER2_HI) XE_GPU_REGISTER(0x0F0E, kDword, BC_PERFCOUNTER3_LOW) XE_GPU_REGISTER(0x0F0F, kDword, BC_PERFCOUNTER3_HI) -// src is flash_xam.xex -// XE_GPU_REGISTER(0x0F12, RB_SIDEBAND_DATA, - +XE_GPU_REGISTER(0x0F10, kDword, RB_ZPASS_SAMPLES) +XE_GPU_REGISTER(0x0F11, kDword, RB_ZFAIL_SAMPLES) +XE_GPU_REGISTER(0x0F12, kDword, RB_SFAIL_SAMPLES) +XE_GPU_REGISTER(0x0F15, kDword, BC_DUMMY_CRAYRB_ENUMS) +XE_GPU_REGISTER(0x0F16, kDword, BC_DUMMY_CRAYRB_MOREENUMS) +XE_GPU_REGISTER(0x0F26, kDword, RB_DEBUG_CNTL) +XE_GPU_REGISTER(0x0F27, kDword, RB_DEBUG_DATA) +XE_GPU_REGISTER(0x0F28, kDword, RB_DEBUG_0) +XE_GPU_REGISTER(0x0F29, kDword, RB_DEBUG_1) +XE_GPU_REGISTER(0x0F2A, kDword, RB_DEBUG_2) +XE_GPU_REGISTER(0x0F2B, kDword, RB_FLAG_CONTROL) +XE_GPU_REGISTER(0x0F2C, kDword, RB_BC_SPARES) XE_GPU_REGISTER(0x1004, kDword, HZ_PERFCOUNTER0_SELECT) XE_GPU_REGISTER(0x1005, kDword, HZ_PERFCOUNTER0_HI) XE_GPU_REGISTER(0x1006, kDword, HZ_PERFCOUNTER0_LOW) XE_GPU_REGISTER(0x1007, kDword, HZ_PERFCOUNTER1_SELECT) XE_GPU_REGISTER(0x1008, kDword, HZ_PERFCOUNTER1_HI) XE_GPU_REGISTER(0x1009, kDword, HZ_PERFCOUNTER1_LOW) - -// D1*, LUT, and AVIVO registers taken from libxenon and -// https://www.x.org/docs/AMD/old/RRG-216M56-03oOEM.pdf +XE_GPU_REGISTER(0x1800, kDword, D1CRTC_H_TOTAL) +XE_GPU_REGISTER(0x1801, kDword, D1CRTC_H_BLANK_START_END) +XE_GPU_REGISTER(0x1802, kDword, D1CRTC_H_SYNC_A) +XE_GPU_REGISTER(0x1803, kDword, D1CRTC_H_SYNC_A_CNTL) +XE_GPU_REGISTER(0x1804, kDword, D1CRTC_V_TOTAL) +XE_GPU_REGISTER(0x1805, kDword, D1CRTC_V_BLANK_START_END) +XE_GPU_REGISTER(0x1806, kDword, D1CRTC_V_SYNC_A) +XE_GPU_REGISTER(0x1807, kDword, D1CRTC_V_SYNC_A_CNTL) +XE_GPU_REGISTER(0x1808, kDword, D1CRTC_FORCE_COUNT_NOW_CNTL) +XE_GPU_REGISTER(0x1809, kDword, D1CRTC_PIXEL_DATA_READBACK) +XE_GPU_REGISTER(0x180A, kDword, D1CRTC_CONTROL) +XE_GPU_REGISTER(0x180B, kDword, D1CRTC_BLANK_CONTROL) +XE_GPU_REGISTER(0x180C, kDword, D1CRTC_INTERLACE_CONTROL) +XE_GPU_REGISTER(0x180D, kDword, D1CRTC_INTERLACE_STATUS) +XE_GPU_REGISTER(0x180E, kDword, D1CRTC_BLANK_DATA_COLOR) +XE_GPU_REGISTER(0x180F, kDword, D1CRTC_OVERSCAN_COLOR) +XE_GPU_REGISTER(0x1810, kDword, D1CRTC_BLACK_COLOR) +XE_GPU_REGISTER(0x1811, kDword, D1CRTC_OVERSCAN_TOP) +XE_GPU_REGISTER(0x1812, kDword, D1CRTC_OVERSCAN_BOTTOM) +XE_GPU_REGISTER(0x1813, kDword, D1CRTC_OVERSCAN_LEFT) +XE_GPU_REGISTER(0x1814, kDword, D1CRTC_OVERSCAN_RIGHT) +XE_GPU_REGISTER(0x1815, kDword, D1CRTC_STATUS) +XE_GPU_REGISTER(0x1816, kDword, D1CRTC_STATUS_POSITION) +XE_GPU_REGISTER(0x1817, kDword, D1CRTC_FRAME_COUNT_CONTROL) +XE_GPU_REGISTER(0x1818, kDword, D1CRTC_STATUS_FRAME_COUNT) +XE_GPU_REGISTER(0x1819, kDword, D1CRTC_STATUS_VF_COUNT) +XE_GPU_REGISTER(0x181A, kDword, D1CRTC_STATUS_HV_COUNT) +XE_GPU_REGISTER(0x181B, kDword, D1CRTC_FRAME_COUNT_START) +XE_GPU_REGISTER(0x181C, kDword, D1CRTC_COUNT_CONTROL) +XE_GPU_REGISTER(0x181D, kDword, D1CRTC_STEREO_STATUS) +XE_GPU_REGISTER(0x181E, kDword, D1CRTC_STEREO_CONTROL) +XE_GPU_REGISTER(0x181F, kDword, D1CRTC_FRAME_RESET_CONTRO) XE_GPU_REGISTER(0x1838, kDword, D1MODE_MASTER_UPDATE_LOCK) +XE_GPU_REGISTER(0x1839, kDword, D1MODE_MASTER_UPDATE_MODE) +XE_GPU_REGISTER(0x183A, kDword, D1CRTC_UPDATE_LOCK) +XE_GPU_REGISTER(0x183B, kDword, D1CRTC_DOUBLE_BUFFER_CONTROL) +XE_GPU_REGISTER(0x183C, kDword, CRTC_DEBUG) +XE_GPU_REGISTER(0x1840, kDword, D1GRPH_ENABLE) XE_GPU_REGISTER(0x1841, kDword, D1GRPH_CONTROL) +XE_GPU_REGISTER(0x1842, kDword, D1GRPH_LUT_10BIT_BYPASS_CNTL) +XE_GPU_REGISTER(0x1843, kDword, D1GRPH_LUT_AFTER_CSC) XE_GPU_REGISTER(0x1844, kDword, D1GRPH_PRIMARY_SURFACE_ADDRESS) +XE_GPU_REGISTER(0x1846, kDword, D1GRPH_SECONDARY_SURFACE_ADDRESS) +XE_GPU_REGISTER(0x1848, kDword, D1GRPH_PITCH) +XE_GPU_REGISTER(0x1849, kDword, D1GRPH_SURFACE_OFFSET_X) +XE_GPU_REGISTER(0x184A, kDword, D1GRPH_SURFACE_OFFSET_Y) +XE_GPU_REGISTER(0x184B, kDword, D1GRPH_X_START) +XE_GPU_REGISTER(0x184C, kDword, D1GRPH_Y_START) +XE_GPU_REGISTER(0x184D, kDword, D1GRPH_X_END) +XE_GPU_REGISTER(0x184E, kDword, D1GRPH_Y_END) +XE_GPU_REGISTER(0x184F, kDword, D1COLOR_SUBSAMPLE_CRCB_CNTL) +XE_GPU_REGISTER(0x1851, kDword, D1GRPH_UPDATE) XE_GPU_REGISTER(0x1852, kDword, D1GRPH_FLIP_CONTROL) // In 4B4F07FE, the 256-entry gamma ramp for the 8bpc framebuffer is set to @@ -428,6 +1016,31 @@ XE_GPU_REGISTER(0x1852, kDword, D1GRPH_FLIP_CONTROL) // Read / write mode in bit 0: 0 - 256-entry table, 1 - PWL. // Default: 0x00000000. +XE_GPU_REGISTER(0x1860, kDword, D1OVL_ENABLE) +XE_GPU_REGISTER(0x1861, kDword, D1OVL_CONTROL1) +XE_GPU_REGISTER(0x1864, kDword, D1OVL_SURFACE_ADDRESS) +XE_GPU_REGISTER(0x1866, kDword, D1OVL_PITCH) +XE_GPU_REGISTER(0x1867, kDword, D1OVL_SURFACE_OFFSET_X) +XE_GPU_REGISTER(0x1868, kDword, D1OVL_SURFACE_OFFSET_Y) +XE_GPU_REGISTER(0x1869, kDword, D1OVL_START) +XE_GPU_REGISTER(0x186A, kDword, D1OVL_END) +XE_GPU_REGISTER(0x186B, kDword, D1OVL_UPDATE) +XE_GPU_REGISTER(0x18C1, kDword, D1OVL_ALPHA_OUTSIDE_OVL_WINDOW) +XE_GPU_REGISTER(0x18C2, kDword, D1OVL_ALPHA_INSIDE_OVL_WINDOW) +XE_GPU_REGISTER(0x18C3, kDword, D1OVL_ALPHA_CONTROL) +XE_GPU_REGISTER(0x18E0, kDword, D1GRPH_COLOR_MATRIX_CNTL) +XE_GPU_REGISTER(0x18E1, kDword, D1GRPH_COLOR_MATRIX_COEF_1_1) +XE_GPU_REGISTER(0x18E2, kDword, D1GRPH_COLOR_MATRIX_COEF_1_2) +XE_GPU_REGISTER(0x18E3, kDword, D1GRPH_COLOR_MATRIX_COEF_1_3) +XE_GPU_REGISTER(0x18E4, kDword, D1GRPH_COLOR_MATRIX_COEF_1_4) +XE_GPU_REGISTER(0x18E5, kDword, D1GRPH_COLOR_MATRIX_COEF_2_1) +XE_GPU_REGISTER(0x18E6, kDword, D1GRPH_COLOR_MATRIX_COEF_2_2) +XE_GPU_REGISTER(0x18E7, kDword, D1GRPH_COLOR_MATRIX_COEF_2_3) +XE_GPU_REGISTER(0x18E8, kDword, D1GRPH_COLOR_MATRIX_COEF_2_4) +XE_GPU_REGISTER(0x18E9, kDword, D1GRPH_COLOR_MATRIX_COEF_3_1) +XE_GPU_REGISTER(0x18EA, kDword, D1GRPH_COLOR_MATRIX_COEF_3_2) +XE_GPU_REGISTER(0x18EB, kDword, D1GRPH_COLOR_MATRIX_COEF_3_3) +XE_GPU_REGISTER(0x18EC, kDword, D1GRPH_COLOR_MATRIX_COEF_3_4) XE_GPU_REGISTER(0x1921, kDword, DC_LUT_RW_MODE) // Read / write index. No lower and upper halves on the Xenos apparently, for // the 256-entry table, the bits 0:7 are the index directly (unlike on the M56, @@ -479,14 +1092,125 @@ XE_GPU_REGISTER(0x1927, kDword, DC_LUT_WRITE_EN_MASK) // Default: 0x00000000. XE_GPU_REGISTER(0x1930, kDword, DC_LUTA_CONTROL) +XE_GPU_REGISTER(0x1931, kDword, DC_LUTA_BLACK_OFFSET_BLUE) +XE_GPU_REGISTER(0x1932, kDword, DC_LUTA_BLACK_OFFSET_GREEN) +XE_GPU_REGISTER(0x1933, kDword, DC_LUTA_BLACK_OFFSET_RED) +XE_GPU_REGISTER(0x1934, kDword, DC_LUTA_WHITE_OFFSET_BLUE) +XE_GPU_REGISTER(0x1935, kDword, DC_LUTA_WHITE_OFFSET_GREEN) +XE_GPU_REGISTER(0x1936, kDword, DC_LUTA_WHITE_OFFSET_RED) +XE_GPU_REGISTER(0x1949, kDword, D1MODE_UNDERFLOW_STATUS) +XE_GPU_REGISTER(0x194A, kDword, D1MODE_DATA_FORMAT) +XE_GPU_REGISTER(0x194B, kDword, D1MODE_DESKTOP_HEIGHT) XE_GPU_REGISTER(0x194C, kDword, D1MODE_V_COUNTER) - -XE_GPU_REGISTER(0x1961, kDword, AVIVO_D1MODE_VIEWPORT_SIZE) - -XE_GPU_REGISTER(0x1964, kDword, AVIVO_D1SCL_SCALER_ENABLE) - -XE_GPU_REGISTER(0x1973, kDword, AVIVO_D1SCL_UPDATE) - +XE_GPU_REGISTER(0x194D, kDword, D1MODE_VBLANK_STATUS) +XE_GPU_REGISTER(0x194E, kDword, D1MODE_VLINE_START_END) +XE_GPU_REGISTER(0x194F, kDword, D1MODE_VLINE_STATUS) +XE_GPU_REGISTER(0x1950, kDword, D1MODE_INT_MASK) +XE_GPU_REGISTER(0x1951, kDword, D1MODE_VBLANK_VLINE_STATUS) +XE_GPU_REGISTER(0x1952, kDword, D1MODE_MAX_CHUNK_SIZE) +XE_GPU_REGISTER(0x1953, kDword, D1MODE_CHUNK_SIZE_DEBUG) +XE_GPU_REGISTER(0x1954, kDword, D1MODE_PRIORITY_A_CNT) +XE_GPU_REGISTER(0x1955, kDword, D1MODE_URGENCY_STAT) +XE_GPU_REGISTER(0x195E, kDword, D1SCL_COEF_RAM_SELECT) +XE_GPU_REGISTER(0x195F, kDword, D1SCL_COEF_RAM_TAP_DATA) +XE_GPU_REGISTER(0x1960, kDword, D1MODE_VIEWPORT_START) +XE_GPU_REGISTER(0x1961, kDword, D1MODE_VIEWPORT_SIZE) +XE_GPU_REGISTER(0x1964, kDword, D1SCL_SCALER_ENABLE) +XE_GPU_REGISTER(0x1965, kDword, D1SCL_TAP_CONTROL) +XE_GPU_REGISTER(0x1968, kDword, D1SCL_MANUAL_REPLICATE_CONTROL) +XE_GPU_REGISTER(0x196C, kDword, D1SCL_HORZ_FILTER_CONTROL) +XE_GPU_REGISTER(0x196D, kDword, D1SCL_HORZ_FILTER_SCALE_RATIO) +XE_GPU_REGISTER(0x196E, kDword, D1SCL_HORZ_FILTER_INIT_RGB_LUMA) +XE_GPU_REGISTER(0x196F, kDword, D1SCL_HORZ_FILTER_INIT_CHROMA) +XE_GPU_REGISTER(0x1970, kDword, D1SCL_VERT_FILTER_CONTROL) +XE_GPU_REGISTER(0x1971, kDword, D1SCL_VERT_FILTER_SCALE_RATIO) +XE_GPU_REGISTER(0x1972, kDword, D1SCL_VERT_FILTER_INIT) +XE_GPU_REGISTER(0x1973, kDword, D1SCL_UPDATE) +XE_GPU_REGISTER(0x1974, kDword, D1SCL_UNDERFLOW_STATUS) +XE_GPU_REGISTER(0x1977, kDword, D1SCL_VERT_FILTER_INIT_BOT) +XE_GPU_REGISTER(0x1978, kDword, D1SCL_COEF_RAM_CONFLICT_STATUS) +XE_GPU_REGISTER(0x1979, kDword, D1SCL_ONE_SHOT_WATERMARK) +XE_GPU_REGISTER(0x197A, kDword, D1MODE_LB_PITCH_IN_WORDS) +XE_GPU_REGISTER(0x198C, kDword, DISP_RBBMIF_RDWR_TIMEOUT) +XE_GPU_REGISTER(0x19BA, kDword, D1SCL_CRC_ENABLE) +XE_GPU_REGISTER(0x19BC, kDword, D1SCL_CRC_SOURCE_SEL) +XE_GPU_REGISTER(0x19BD, kDword, D1SCL_CRC_MAS) +XE_GPU_REGISTER(0x19BE, kDword, D1SCL_CRC_CURRENT) +XE_GPU_REGISTER(0x19BF, kDword, D1SCL_CRC_LAST) +XE_GPU_REGISTER(0x1B20, kDword, DCP_CRC_CONTROL) +XE_GPU_REGISTER(0x1B21, kDword, DCP_CRC_MASK) +XE_GPU_REGISTER(0x1B22, kDword, DCP_CRC_P0_CURRENT) +XE_GPU_REGISTER(0x1B24, kDword, DCP_CRC_P0_LAST) +XE_GPU_REGISTER(0x1B25, kDword, DCP_DEBUG) +XE_GPU_REGISTER(0x1B2E, kDword, DMIF_STATUS) +XE_GPU_REGISTER(0x1B2F, kDword, DCP_LB_DATA_GAP_BETWEEN_CHUNK) +XE_GPU_REGISTER(0x1C46, kDword, DC_LB_MEM_SIZE) +XE_GPU_REGISTER(0x1E40, kDword, XDVO_ENABLE) +XE_GPU_REGISTER(0x1E43, kDword, XDVO_BIT_DEPTH_CONTROL) +XE_GPU_REGISTER(0x1E44, kDword, XDVO_CLOCK_INV) +XE_GPU_REGISTER(0x1E45, kDword, XDVO_CONTROL) +XE_GPU_REGISTER(0x1E46, kDword, XDVO_CRC_EN) +XE_GPU_REGISTER(0x1E47, kDword, XDVO_CRC_CNTL) +XE_GPU_REGISTER(0x1E48, kDword, XDVO_CRC_MASK_SIG_RGB) +XE_GPU_REGISTER(0x1E49, kDword, XDVO_CRC_MASK_SIG_CNTL) +XE_GPU_REGISTER(0x1E4A, kDword, XDVO_CRC_SIG_RGB) +XE_GPU_REGISTER(0x1E4B, kDword, XDVO_CRC_SIG_CNTL) +XE_GPU_REGISTER(0x1E4C, kDword, XDVO_STRENGTH_CONTROL) +XE_GPU_REGISTER(0x1E4D, kDword, XDVO_DATA_STRENGTH_CONTROL) +XE_GPU_REGISTER(0x1E4E, kDword, XDVO_FORCE_OUTPUT_CNTL) +XE_GPU_REGISTER(0x1E4F, kDword, XDVO_FORCE_DATA) +XE_GPU_REGISTER(0x1E50, kDword, XDVO_2ND_CRC_EN) +XE_GPU_REGISTER(0x1E51, kDword, XDVO_2ND_CRC_CNTL) +XE_GPU_REGISTER(0x1E52, kDword, XDVO_2ND_CRC_MASK_SIG) +XE_GPU_REGISTER(0x1E53, kDword, XDVO_2ND_CRC_SIG) +XE_GPU_REGISTER(0x1E54, kDword, XDVO_REGISTER_INDEX) +XE_GPU_REGISTER(0x1E55, kDword, XDVO_REGISTER_DATA) +XE_GPU_REGISTER(0x1F98, kDword, DC_GPIO_XDVODATA_MASK) +XE_GPU_REGISTER(0x1F99, kDword, DC_GPIO_XDVODATA_A) +XE_GPU_REGISTER(0x1F9A, kDword, DC_GPIO_XDVODATA_EN) +XE_GPU_REGISTER(0x1F9B, kDword, DC_GPIO_XDVODATA_Y) +XE_GPU_REGISTER(0x1F9C, kDword, DC_HSYNC_DEBUG_TEST) +XE_GPU_REGISTER(0x1FB4, kDword, CAPTURE_START_STATUS) +XE_GPU_REGISTER(0x1FB7, kDword, DISP_INTERRUPT_STATUS) +XE_GPU_REGISTER(0x1FB8, kDword, DOUT_DEBUG) +XE_GPU_REGISTER(0x1FC0, kDword, DO_PERFCOUNTER0_SELECT) +XE_GPU_REGISTER(0x1FC1, kDword, DO_PERFCOUNTER0_HI) +XE_GPU_REGISTER(0x1FC2, kDword, DO_PERFCOUNTER0_LOW) +XE_GPU_REGISTER(0x1FC3, kDword, DO_PERFCOUNTER1_SELECT) +XE_GPU_REGISTER(0x1FC4, kDword, DO_PERFCOUNTER1_HI) +XE_GPU_REGISTER(0x1FC5, kDword, DO_PERFCOUNTER1_LOW) +XE_GPU_REGISTER(0x1FC8, kDword, DC_PERFCOUNTER0_SELECT) +XE_GPU_REGISTER(0x1FC9, kDword, DC_PERFCOUNTER0_HI) +XE_GPU_REGISTER(0x1FCA, kDword, DC_PERFCOUNTER0_LOW) +XE_GPU_REGISTER(0x1FCB, kDword, DC_PERFCOUNTER1_SELECT) +XE_GPU_REGISTER(0x1FCC, kDword, DC_PERFCOUNTER1_HI) +XE_GPU_REGISTER(0x1FCD, kDword, DC_PERFCOUNTER1_LOW) +XE_GPU_REGISTER(0x1FCE, kDword, DC_PERFMON_CNTL) +XE_GPU_REGISTER(0x1FD0, kDword, DC_DOUT_DEBUG_MUX_CNTL) +XE_GPU_REGISTER(0x1FE6, kDword, DC_TEST_DEBUG_BUS_CLK1_SEL) +XE_GPU_REGISTER(0x1FE7, kDword, DC_TEST_DEBUG_OUT_PIN_MASK) +XE_GPU_REGISTER(0x1FE8, kDword, DC_TEST_DEBUG_TRIGGER_CNTL) +XE_GPU_REGISTER(0x1FE9, kDword, DC_TEST_DEBUG_TRIGGER_STAT) +XE_GPU_REGISTER(0x1FEA, kDword, DC_TEST_DEBUG_EDGE_TRIGGER_MASK) +XE_GPU_REGISTER(0x1FEB, kDword, DC_TEST_DEBUG_EDGE_TRIGGER_PATTERN) +XE_GPU_REGISTER(0x1FEC, kDword, DC_TEST_DEBUG_DATA_TRIGGER_MASK) +XE_GPU_REGISTER(0x1FED, kDword, DC_TEST_DEBUG_DATA_TRIGGER_PATTERN) +XE_GPU_REGISTER(0x1FEE, kDword, DC_TEST_DEBUG_OUT_TEST_DATA) +XE_GPU_REGISTER(0x1FEF, kDword, DC_TEST_DEBUG_OUT_CNTL) +XE_GPU_REGISTER(0x1FF2, kDword, DO_TEST_DEBUG_BUS_CLK1_SEL) +XE_GPU_REGISTER(0x1FF3, kDword, DO_TEST_DEBUG_OUT_PIN_MASK) +XE_GPU_REGISTER(0x1FF4, kDword, DO_TEST_DEBUG_TRIGGER_CNTL) +XE_GPU_REGISTER(0x1FF5, kDword, DO_TEST_DEBUG_TRIGGER_STAT) +XE_GPU_REGISTER(0x1FF6, kDword, DO_TEST_DEBUG_EDGE_TRIGGER_MASK) +XE_GPU_REGISTER(0x1FF7, kDword, DO_TEST_DEBUG_EDGE_TRIGGER_PATTERN) +XE_GPU_REGISTER(0x1FF8, kDword, DO_TEST_DEBUG_DATA_TRIGGER_MASK) +XE_GPU_REGISTER(0x1FF9, kDword, DO_TEST_DEBUG_DATA_TRIGGER_PATTERN) +XE_GPU_REGISTER(0x1FFA, kDword, DO_TEST_DEBUG_OUT_TEST_DATA) +XE_GPU_REGISTER(0x1FFB, kDword, DO_TEST_DEBUG_OUT_CNTL) +XE_GPU_REGISTER(0x1FFC, kDword, DC_TEST_DEBUG_INDEX) +XE_GPU_REGISTER(0x1FFD, kDword, DC_TEST_DEBUG_DATA) +XE_GPU_REGISTER(0x1FFE, kDword, DO_TEST_DEBUG_INDEX) +XE_GPU_REGISTER(0x1FFF, kDword, DO_TEST_DEBUG_DATA) XE_GPU_REGISTER(0x2000, kDword, RB_SURFACE_INFO) XE_GPU_REGISTER(0x2001, kDword, RB_COLOR_INFO) XE_GPU_REGISTER(0x2002, kDword, RB_DEPTH_INFO) @@ -508,6 +1232,15 @@ XE_GPU_REGISTER(0x2080, kDword, PA_SC_WINDOW_OFFSET) XE_GPU_REGISTER(0x2081, kDword, PA_SC_WINDOW_SCISSOR_TL) XE_GPU_REGISTER(0x2082, kDword, PA_SC_WINDOW_SCISSOR_BR) +XE_GPU_REGISTER(0x2083, kDword, PA_SC_CLIPRECT_RULE) +XE_GPU_REGISTER(0x2084, kDword, PA_SC_CLIPRECT_0_TL) +XE_GPU_REGISTER(0x2085, kDword, PA_SC_CLIPRECT_0_BR) +XE_GPU_REGISTER(0x2086, kDword, PA_SC_CLIPRECT_1_TL) +XE_GPU_REGISTER(0x2087, kDword, PA_SC_CLIPRECT_1_BR) +XE_GPU_REGISTER(0x2088, kDword, PA_SC_CLIPRECT_2_TL) +XE_GPU_REGISTER(0x2089, kDword, PA_SC_CLIPRECT_2_BR) +XE_GPU_REGISTER(0x208A, kDword, PA_SC_CLIPRECT_3_TL) +XE_GPU_REGISTER(0x208B, kDword, PA_SC_CLIPRECT_3_BR) XE_GPU_REGISTER(0x2100, kDword, VGT_MAX_VTX_INDX) XE_GPU_REGISTER(0x2101, kDword, VGT_MIN_VTX_INDX) XE_GPU_REGISTER(0x2102, kDword, VGT_INDX_OFFSET) @@ -535,8 +1268,10 @@ XE_GPU_REGISTER(0x2181, kDword, SQ_CONTEXT_MISC) XE_GPU_REGISTER(0x2182, kDword, SQ_INTERPOLATOR_CNTL) XE_GPU_REGISTER(0x2183, kDword, SQ_WRAPPING_0) XE_GPU_REGISTER(0x2184, kDword, SQ_WRAPPING_1) - -// These three registers are set by the command processor. +XE_GPU_REGISTER(0x21F4, kDword, GFX_COPY_STATE) +XE_GPU_REGISTER(0x21F5, kDword, SQ_CF_RD_BASE) +XE_GPU_REGISTER(0x21F6, kDword, SQ_PS_PROGRAM) +XE_GPU_REGISTER(0x21F7, kDword, SQ_VS_PROGRAM) XE_GPU_REGISTER(0x21F9, kDword, VGT_EVENT_INITIATOR) XE_GPU_REGISTER(0x21FA, kDword, VGT_DMA_BASE) XE_GPU_REGISTER(0x21FB, kDword, VGT_DMA_SIZE) @@ -556,6 +1291,7 @@ XE_GPU_REGISTER(0x2209, kDword, RB_BLENDCONTROL1) XE_GPU_REGISTER(0x220A, kDword, RB_BLENDCONTROL2) XE_GPU_REGISTER(0x220B, kDword, RB_BLENDCONTROL3) +XE_GPU_REGISTER(0x2210, kDword, GRAS_CONTROL) XE_GPU_REGISTER(0x2280, kDword, PA_SU_POINT_SIZE) XE_GPU_REGISTER(0x2281, kDword, PA_SU_POINT_MINMAX) XE_GPU_REGISTER(0x2282, kDword, PA_SU_LINE_CNTL) @@ -616,12 +1352,10 @@ XE_GPU_REGISTER(0x2322, kDword, RB_COPY_MASK) XE_GPU_REGISTER(0x2323, kDword, RB_COPY_SURFACE_SLICE) XE_GPU_REGISTER(0x2324, kDword, RB_SAMPLE_COUNT_CTL) XE_GPU_REGISTER(0x2325, kDword, RB_SAMPLE_COUNT_ADDR) - -// Polygon offset scales and offsets are 32-bit floating-point. -// "slope computed in subpixels (1/12 or 1/16)" - R5xx Acceleration. -// But the correct scale for conversion of the slope scale (FRONT_BACK/SCALE) -// from subpixels to pixels is likely 1/16 according to: -// https://github.com/mesa3d/mesa/blob/54ad9b444c8e73da498211870e785239ad3ff1aa/src/gallium/drivers/radeonsi/si_state.c#L946 +XE_GPU_REGISTER(0x2326, kFloat, RB_COLOR_DEST_MASK) +XE_GPU_REGISTER(0x2340, kFloat, GRAS_UCP0X) +XE_GPU_REGISTER(0x2357, kFloat, GRAS_UCP5W) +XE_GPU_REGISTER(0x2360, kFloat, GRAS_UCP_ENABLED) XE_GPU_REGISTER(0x2380, kFloat, PA_SU_POLY_OFFSET_FRONT_SCALE) XE_GPU_REGISTER(0x2381, kFloat, PA_SU_POLY_OFFSET_FRONT_OFFSET) XE_GPU_REGISTER(0x2382, kFloat, PA_SU_POLY_OFFSET_BACK_SCALE)