From 5ec0c926015a9b5ae711df9e8c3b4542fe515b87 Mon Sep 17 00:00:00 2001 From: Triang3l Date: Wed, 27 Apr 2022 21:46:29 +0300 Subject: [PATCH] [GPU] Ignore z_enable for !z_write_enable && z_func == ALWAYS --- .../gpu/d3d12/d3d12_command_processor.cc | 49 +++++++++++-------- src/xenia/gpu/d3d12/d3d12_command_processor.h | 5 +- .../gpu/d3d12/d3d12_render_target_cache.cc | 6 ++- .../gpu/d3d12/d3d12_render_target_cache.h | 1 + src/xenia/gpu/d3d12/pipeline_cache.cc | 44 ++++++++++------- src/xenia/gpu/d3d12/pipeline_cache.h | 6 ++- src/xenia/gpu/draw_util.cc | 24 ++++++++- src/xenia/gpu/draw_util.h | 14 +----- src/xenia/gpu/render_target_cache.cc | 7 +-- src/xenia/gpu/render_target_cache.h | 4 +- 10 files changed, 100 insertions(+), 60 deletions(-) diff --git a/src/xenia/gpu/d3d12/d3d12_command_processor.cc b/src/xenia/gpu/d3d12/d3d12_command_processor.cc index 79bcd5da9..2f06cfe54 100644 --- a/src/xenia/gpu/d3d12/d3d12_command_processor.cc +++ b/src/xenia/gpu/d3d12/d3d12_command_processor.cc @@ -22,6 +22,7 @@ #include "xenia/gpu/d3d12/d3d12_shader.h" #include "xenia/gpu/draw_util.h" #include "xenia/gpu/gpu_flags.h" +#include "xenia/gpu/registers.h" #include "xenia/gpu/xenos.h" #include "xenia/ui/d3d12/d3d12_presenter.h" #include "xenia/ui/d3d12/d3d12_util.h" @@ -2127,14 +2128,17 @@ bool D3D12CommandProcessor::IssueDraw(xenos::PrimitiveType primitive_type, return true; } + reg::RB_DEPTHCONTROL normalized_depth_control = + draw_util::GetNormalizedDepthControl(regs); + // Shader modifications. DxbcShaderTranslator::Modification vertex_shader_modification = pipeline_cache_->GetCurrentVertexShaderModification( *vertex_shader, primitive_processing_result.host_vertex_shader_type); DxbcShaderTranslator::Modification pixel_shader_modification = - pixel_shader - ? pipeline_cache_->GetCurrentPixelShaderModification(*pixel_shader) - : DxbcShaderTranslator::Modification(0); + pixel_shader ? pipeline_cache_->GetCurrentPixelShaderModification( + *pixel_shader, normalized_depth_control) + : DxbcShaderTranslator::Modification(0); // Set up the render targets - this may perform dispatches and draws. uint32_t normalized_color_mask = @@ -2142,6 +2146,7 @@ bool D3D12CommandProcessor::IssueDraw(xenos::PrimitiveType primitive_type, regs, pixel_shader->writes_color_targets()) : 0; if (!render_target_cache_->Update(is_rasterization_done, + normalized_depth_control, normalized_color_mask)) { return false; } @@ -2173,8 +2178,8 @@ bool D3D12CommandProcessor::IssueDraw(xenos::PrimitiveType primitive_type, ID3D12RootSignature* root_signature; if (!pipeline_cache_->ConfigurePipeline( vertex_shader_translation, pixel_shader_translation, - primitive_processing_result, normalized_color_mask, - bound_depth_and_color_render_target_bits, + primitive_processing_result, normalized_depth_control, + normalized_color_mask, bound_depth_and_color_render_target_bits, bound_depth_and_color_render_target_formats, &pipeline_handle, &root_signature)) { return false; @@ -2206,6 +2211,7 @@ bool D3D12CommandProcessor::IssueDraw(xenos::PrimitiveType primitive_type, draw_util::GetHostViewportInfo( regs, resolution_scale_x, resolution_scale_y, true, D3D12_VIEWPORT_BOUNDS_MAX, D3D12_VIEWPORT_BOUNDS_MAX, false, + normalized_depth_control, host_render_targets_used && (depth_float24_conversion == RenderTargetCache::DepthFloat24Conversion::kOnOutputTruncating || @@ -2221,7 +2227,8 @@ bool D3D12CommandProcessor::IssueDraw(xenos::PrimitiveType primitive_type, scissor.extent[1] *= resolution_scale_y; // Update viewport, scissor, blend factor and stencil reference. - UpdateFixedFunctionState(viewport_info, scissor, primitive_polygonal); + UpdateFixedFunctionState(viewport_info, scissor, primitive_polygonal, + normalized_depth_control); // Update system constants before uploading them. // TODO(Triang3l): With ROV, pass the disabled render target mask for safety. @@ -2229,7 +2236,7 @@ bool D3D12CommandProcessor::IssueDraw(xenos::PrimitiveType primitive_type, memexport_used, primitive_polygonal, primitive_processing_result.line_loop_closing_index, primitive_processing_result.host_index_endian, viewport_info, - used_texture_mask, normalized_color_mask); + used_texture_mask, normalized_depth_control, normalized_color_mask); // Update constant buffers, descriptors and root parameters. if (!UpdateBindings(vertex_shader, pixel_shader, root_signature)) { @@ -3029,7 +3036,8 @@ void D3D12CommandProcessor::ClearCommandAllocatorCache() { void D3D12CommandProcessor::UpdateFixedFunctionState( const draw_util::ViewportInfo& viewport_info, - const draw_util::Scissor& scissor, bool primitive_polygonal) { + const draw_util::Scissor& scissor, bool primitive_polygonal, + reg::RB_DEPTHCONTROL normalized_depth_control) { #if XE_UI_D3D12_FINE_GRAINED_DRAW_SCOPES SCOPE_profile_cpu_f("gpu"); #endif // XE_UI_D3D12_FINE_GRAINED_DRAW_SCOPES @@ -3077,8 +3085,7 @@ void D3D12CommandProcessor::UpdateFixedFunctionState( // choose the back face one only if drawing only back faces. Register stencil_ref_mask_reg; auto pa_su_sc_mode_cntl = regs.Get(); - if (primitive_polygonal && - draw_util::GetDepthControlForCurrentEdramMode(regs).backface_enable && + if (primitive_polygonal && normalized_depth_control.backface_enable && pa_su_sc_mode_cntl.cull_front && !pa_su_sc_mode_cntl.cull_back) { stencil_ref_mask_reg = XE_GPU_REG_RB_STENCILREFMASK_BF; } else { @@ -3099,6 +3106,7 @@ void D3D12CommandProcessor::UpdateSystemConstantValues( bool shared_memory_is_uav, bool primitive_polygonal, uint32_t line_loop_closing_index, xenos::Endian index_endian, const draw_util::ViewportInfo& viewport_info, uint32_t used_texture_mask, + reg::RB_DEPTHCONTROL normalized_depth_control, uint32_t normalized_color_mask) { #if XE_UI_D3D12_FINE_GRAINED_DRAW_SCOPES SCOPE_profile_cpu_f("gpu"); @@ -3113,7 +3121,6 @@ void D3D12CommandProcessor::UpdateSystemConstantValues( float rb_alpha_ref = regs[XE_GPU_REG_RB_ALPHA_REF].f32; auto rb_colorcontrol = regs.Get(); auto rb_depth_info = regs.Get(); - auto rb_depthcontrol = draw_util::GetDepthControlForCurrentEdramMode(regs); auto rb_stencilrefmask = regs.Get(); auto rb_stencilrefmask_bf = regs.Get(XE_GPU_REG_RB_STENCILREFMASK_BF); @@ -3155,8 +3162,8 @@ void D3D12CommandProcessor::UpdateSystemConstantValues( // Disable depth and stencil if it aliases a color render target (for // instance, during the XBLA logo in 58410954, though depth writing is already // disabled there). - bool depth_stencil_enabled = - rb_depthcontrol.stencil_enable || rb_depthcontrol.z_enable; + bool depth_stencil_enabled = normalized_depth_control.stencil_enable || + normalized_depth_control.z_enable; if (edram_rov_used && depth_stencil_enabled) { for (uint32_t i = 0; i < 4; ++i) { if (rb_depth_info.depth_base == color_infos[i].color_base && @@ -3229,10 +3236,10 @@ void D3D12CommandProcessor::UpdateSystemConstantValues( } if (edram_rov_used && depth_stencil_enabled) { flags |= DxbcShaderTranslator::kSysFlag_ROVDepthStencil; - if (rb_depthcontrol.z_enable) { - flags |= uint32_t(rb_depthcontrol.zfunc) + if (normalized_depth_control.z_enable) { + flags |= uint32_t(normalized_depth_control.zfunc) << DxbcShaderTranslator::kSysFlag_ROVDepthPassIfLess_Shift; - if (rb_depthcontrol.z_write_enable) { + if (normalized_depth_control.z_write_enable) { flags |= DxbcShaderTranslator::kSysFlag_ROVDepthWrite; } } else { @@ -3242,7 +3249,7 @@ void D3D12CommandProcessor::UpdateSystemConstantValues( DxbcShaderTranslator::kSysFlag_ROVDepthPassIfEqual | DxbcShaderTranslator::kSysFlag_ROVDepthPassIfGreater; } - if (rb_depthcontrol.stencil_enable) { + if (normalized_depth_control.stencil_enable) { flags |= DxbcShaderTranslator::kSysFlag_ROVStencilTest; } // Hint - if not applicable to the shader, will not have effect. @@ -3526,7 +3533,7 @@ void D3D12CommandProcessor::UpdateSystemConstantValues( poly_offset_back_offset; system_constants_.edram_poly_offset_back_offset = poly_offset_back_offset; - if (depth_stencil_enabled && rb_depthcontrol.stencil_enable) { + if (depth_stencil_enabled && normalized_depth_control.stencil_enable) { dirty |= system_constants_.edram_stencil_front_reference != rb_stencilrefmask.stencilref; system_constants_.edram_stencil_front_reference = @@ -3540,12 +3547,12 @@ void D3D12CommandProcessor::UpdateSystemConstantValues( system_constants_.edram_stencil_front_write_mask = rb_stencilrefmask.stencilwritemask; uint32_t stencil_func_ops = - (rb_depthcontrol.value >> 8) & ((1 << 12) - 1); + (normalized_depth_control.value >> 8) & ((1 << 12) - 1); dirty |= system_constants_.edram_stencil_front_func_ops != stencil_func_ops; system_constants_.edram_stencil_front_func_ops = stencil_func_ops; - if (primitive_polygonal && rb_depthcontrol.backface_enable) { + if (primitive_polygonal && normalized_depth_control.backface_enable) { dirty |= system_constants_.edram_stencil_back_reference != rb_stencilrefmask_bf.stencilref; system_constants_.edram_stencil_back_reference = @@ -3559,7 +3566,7 @@ void D3D12CommandProcessor::UpdateSystemConstantValues( system_constants_.edram_stencil_back_write_mask = rb_stencilrefmask_bf.stencilwritemask; uint32_t stencil_func_ops_bf = - (rb_depthcontrol.value >> 20) & ((1 << 12) - 1); + (normalized_depth_control.value >> 20) & ((1 << 12) - 1); dirty |= system_constants_.edram_stencil_back_func_ops != stencil_func_ops_bf; system_constants_.edram_stencil_back_func_ops = stencil_func_ops_bf; diff --git a/src/xenia/gpu/d3d12/d3d12_command_processor.h b/src/xenia/gpu/d3d12/d3d12_command_processor.h index e5ed3249d..a3b9f8577 100644 --- a/src/xenia/gpu/d3d12/d3d12_command_processor.h +++ b/src/xenia/gpu/d3d12/d3d12_command_processor.h @@ -30,6 +30,7 @@ #include "xenia/gpu/draw_util.h" #include "xenia/gpu/dxbc_shader.h" #include "xenia/gpu/dxbc_shader_translator.h" +#include "xenia/gpu/registers.h" #include "xenia/gpu/xenos.h" #include "xenia/kernel/kernel_state.h" #include "xenia/ui/d3d12/d3d12_descriptor_heap_pool.h" @@ -349,13 +350,15 @@ class D3D12CommandProcessor : public CommandProcessor { void UpdateFixedFunctionState(const draw_util::ViewportInfo& viewport_info, const draw_util::Scissor& scissor, - bool primitive_polygonal); + bool primitive_polygonal, + reg::RB_DEPTHCONTROL normalized_depth_control); void UpdateSystemConstantValues(bool shared_memory_is_uav, bool primitive_polygonal, uint32_t line_loop_closing_index, xenos::Endian index_endian, const draw_util::ViewportInfo& viewport_info, uint32_t used_texture_mask, + reg::RB_DEPTHCONTROL normalized_depth_control, uint32_t normalized_color_mask); bool UpdateBindings(const D3D12Shader* vertex_shader, const D3D12Shader* pixel_shader, diff --git a/src/xenia/gpu/d3d12/d3d12_render_target_cache.cc b/src/xenia/gpu/d3d12/d3d12_render_target_cache.cc index 28c2a610a..b13f8bda1 100644 --- a/src/xenia/gpu/d3d12/d3d12_render_target_cache.cc +++ b/src/xenia/gpu/d3d12/d3d12_render_target_cache.cc @@ -1249,9 +1249,11 @@ void D3D12RenderTargetCache::BeginSubmission() { } } -bool D3D12RenderTargetCache::Update(bool is_rasterization_done, - uint32_t shader_writes_color_targets) { +bool D3D12RenderTargetCache::Update( + bool is_rasterization_done, reg::RB_DEPTHCONTROL normalized_depth_control, + uint32_t shader_writes_color_targets) { if (!RenderTargetCache::Update(is_rasterization_done, + normalized_depth_control, shader_writes_color_targets)) { return false; } diff --git a/src/xenia/gpu/d3d12/d3d12_render_target_cache.h b/src/xenia/gpu/d3d12/d3d12_render_target_cache.h index 7121d47ba..09512838d 100644 --- a/src/xenia/gpu/d3d12/d3d12_render_target_cache.h +++ b/src/xenia/gpu/d3d12/d3d12_render_target_cache.h @@ -64,6 +64,7 @@ class D3D12RenderTargetCache final : public RenderTargetCache { uint32_t GetResolutionScaleY() const override { return resolution_scale_y_; } bool Update(bool is_rasterization_done, + reg::RB_DEPTHCONTROL normalized_depth_control, uint32_t shader_writes_color_targets) override; void InvalidateCommandListRenderTargets() { diff --git a/src/xenia/gpu/d3d12/pipeline_cache.cc b/src/xenia/gpu/d3d12/pipeline_cache.cc index 75a096f48..cf5e3c948 100644 --- a/src/xenia/gpu/d3d12/pipeline_cache.cc +++ b/src/xenia/gpu/d3d12/pipeline_cache.cc @@ -36,6 +36,7 @@ #include "xenia/gpu/d3d12/d3d12_render_target_cache.h" #include "xenia/gpu/draw_util.h" #include "xenia/gpu/gpu_flags.h" +#include "xenia/gpu/registers.h" #include "xenia/gpu/xenos.h" #include "xenia/ui/d3d12/d3d12_util.h" @@ -896,7 +897,8 @@ PipelineCache::GetCurrentVertexShaderModification( } DxbcShaderTranslator::Modification -PipelineCache::GetCurrentPixelShaderModification(const Shader& shader) const { +PipelineCache::GetCurrentPixelShaderModification( + const Shader& shader, reg::RB_DEPTHCONTROL normalized_depth_control) const { assert_true(shader.type() == xenos::ShaderType::kPixel); assert_true(shader.is_ucode_analyzed()); const auto& regs = register_file_; @@ -915,7 +917,7 @@ PipelineCache::GetCurrentPixelShaderModification(const Shader& shader) const { RenderTargetCache::DepthFloat24Conversion::kOnOutputTruncating || depth_float24_conversion == RenderTargetCache::DepthFloat24Conversion::kOnOutputRounding) && - draw_util::GetDepthControlForCurrentEdramMode(regs).z_enable && + normalized_depth_control.z_enable && regs.Get().depth_format == xenos::DepthRenderTargetFormat::kD24FS8) { modification.pixel.depth_stencil_mode = @@ -941,6 +943,7 @@ bool PipelineCache::ConfigurePipeline( D3D12Shader::D3D12Translation* vertex_shader, D3D12Shader::D3D12Translation* pixel_shader, const PrimitiveProcessor::ProcessingResult& primitive_processing_result, + reg::RB_DEPTHCONTROL normalized_depth_control, uint32_t normalized_color_mask, uint32_t bound_depth_and_color_render_target_bits, const uint32_t* bound_depth_and_color_render_target_formats, @@ -1013,7 +1016,8 @@ bool PipelineCache::ConfigurePipeline( PipelineRuntimeDescription runtime_description; if (!GetCurrentStateDescription( vertex_shader, pixel_shader, primitive_processing_result, - normalized_color_mask, bound_depth_and_color_render_target_bits, + normalized_depth_control, normalized_color_mask, + bound_depth_and_color_render_target_bits, bound_depth_and_color_render_target_formats, runtime_description)) { return false; } @@ -1280,6 +1284,7 @@ bool PipelineCache::GetCurrentStateDescription( D3D12Shader::D3D12Translation* vertex_shader, D3D12Shader::D3D12Translation* pixel_shader, const PrimitiveProcessor::ProcessingResult& primitive_processing_result, + reg::RB_DEPTHCONTROL normalized_depth_control, uint32_t normalized_color_mask, uint32_t bound_depth_and_color_render_target_bits, const uint32_t* bound_depth_and_color_render_target_formats, @@ -1483,18 +1488,16 @@ bool PipelineCache::GetCurrentStateDescription( // Depth/stencil. No stencil, always passing depth test and no depth writing // means depth disabled. if (bound_depth_and_color_render_target_bits & 1) { - auto rb_depthcontrol = - draw_util::GetDepthControlForCurrentEdramMode(regs); - if (rb_depthcontrol.z_enable) { - description_out.depth_func = rb_depthcontrol.zfunc; - description_out.depth_write = rb_depthcontrol.z_write_enable; + if (normalized_depth_control.z_enable) { + description_out.depth_func = normalized_depth_control.zfunc; + description_out.depth_write = normalized_depth_control.z_write_enable; } else { description_out.depth_func = xenos::CompareFunction::kAlways; } - if (rb_depthcontrol.stencil_enable) { + if (normalized_depth_control.stencil_enable) { description_out.stencil_enable = 1; bool stencil_backface_enable = - primitive_polygonal && rb_depthcontrol.backface_enable; + primitive_polygonal && normalized_depth_control.backface_enable; // Per-face masks not supported by Direct3D 12, choose the back face // ones only if drawing only back faces. Register stencil_ref_mask_reg; @@ -1507,18 +1510,23 @@ bool PipelineCache::GetCurrentStateDescription( regs.Get(stencil_ref_mask_reg); description_out.stencil_read_mask = stencil_ref_mask.stencilmask; description_out.stencil_write_mask = stencil_ref_mask.stencilwritemask; - description_out.stencil_front_fail_op = rb_depthcontrol.stencilfail; + description_out.stencil_front_fail_op = + normalized_depth_control.stencilfail; description_out.stencil_front_depth_fail_op = - rb_depthcontrol.stencilzfail; - description_out.stencil_front_pass_op = rb_depthcontrol.stencilzpass; - description_out.stencil_front_func = rb_depthcontrol.stencilfunc; + normalized_depth_control.stencilzfail; + description_out.stencil_front_pass_op = + normalized_depth_control.stencilzpass; + description_out.stencil_front_func = + normalized_depth_control.stencilfunc; if (stencil_backface_enable) { - description_out.stencil_back_fail_op = rb_depthcontrol.stencilfail_bf; + description_out.stencil_back_fail_op = + normalized_depth_control.stencilfail_bf; description_out.stencil_back_depth_fail_op = - rb_depthcontrol.stencilzfail_bf; + normalized_depth_control.stencilzfail_bf; description_out.stencil_back_pass_op = - rb_depthcontrol.stencilzpass_bf; - description_out.stencil_back_func = rb_depthcontrol.stencilfunc_bf; + normalized_depth_control.stencilzpass_bf; + description_out.stencil_back_func = + normalized_depth_control.stencilfunc_bf; } else { description_out.stencil_back_fail_op = description_out.stencil_front_fail_op; diff --git a/src/xenia/gpu/d3d12/pipeline_cache.h b/src/xenia/gpu/d3d12/pipeline_cache.h index 2f8f8b02b..74ea0c9e0 100644 --- a/src/xenia/gpu/d3d12/pipeline_cache.h +++ b/src/xenia/gpu/d3d12/pipeline_cache.h @@ -31,6 +31,7 @@ #include "xenia/gpu/gpu_flags.h" #include "xenia/gpu/primitive_processor.h" #include "xenia/gpu/register_file.h" +#include "xenia/gpu/registers.h" #include "xenia/gpu/xenos.h" #include "xenia/ui/d3d12/d3d12_api.h" @@ -74,7 +75,8 @@ class PipelineCache { const Shader& shader, Shader::HostVertexShaderType host_vertex_shader_type) const; DxbcShaderTranslator::Modification GetCurrentPixelShaderModification( - const Shader& shader) const; + const Shader& shader, + reg::RB_DEPTHCONTROL normalized_depth_control) const; // If draw_util::IsRasterizationPotentiallyDone is false, the pixel shader // MUST be made nullptr BEFORE calling this! @@ -82,6 +84,7 @@ class PipelineCache { D3D12Shader::D3D12Translation* vertex_shader, D3D12Shader::D3D12Translation* pixel_shader, const PrimitiveProcessor::ProcessingResult& primitive_processing_result, + reg::RB_DEPTHCONTROL normalized_depth_control, uint32_t normalized_color_mask, uint32_t bound_depth_and_color_render_target_bits, const uint32_t* bound_depth_and_color_render_targets_formats, @@ -248,6 +251,7 @@ class PipelineCache { D3D12Shader::D3D12Translation* vertex_shader, D3D12Shader::D3D12Translation* pixel_shader, const PrimitiveProcessor::ProcessingResult& primitive_processing_result, + reg::RB_DEPTHCONTROL normalized_depth_control, uint32_t normalized_color_mask, uint32_t bound_depth_and_color_render_target_bits, const uint32_t* bound_depth_and_color_render_target_formats, diff --git a/src/xenia/gpu/draw_util.cc b/src/xenia/gpu/draw_util.cc index ba01e4b2f..b79d90c48 100644 --- a/src/xenia/gpu/draw_util.cc +++ b/src/xenia/gpu/draw_util.cc @@ -63,6 +63,27 @@ bool IsRasterizationPotentiallyDone(const RegisterFile& regs, return true; } +reg::RB_DEPTHCONTROL GetNormalizedDepthControl(const RegisterFile& regs) { + xenos::ModeControl edram_mode = regs.Get().edram_mode; + if (edram_mode != xenos::ModeControl::kColorDepth && + edram_mode != xenos::ModeControl::kDepth) { + // Both depth and stencil disabled (EDRAM depth and stencil ignored). + reg::RB_DEPTHCONTROL disabled; + disabled.value = 0; + return disabled; + } + reg::RB_DEPTHCONTROL depthcontrol = regs.Get(); + // For more reliable skipping of depth render target management for draws not + // requiring depth. + if (depthcontrol.z_enable && !depthcontrol.z_write_enable && + depthcontrol.zfunc == xenos::CompareFunction::kAlways) { + depthcontrol.z_enable = 0; + } + // Stencil is more complex and is expected to be usually enabled explicitly + // when needed. + return depthcontrol; +} + // https://docs.microsoft.com/en-us/windows/win32/api/d3d11/ne-d3d11-d3d11_standard_multisample_quality_levels const int8_t kD3D10StandardSamplePositions2x[2][2] = {{4, 4}, {-4, -4}}; const int8_t kD3D10StandardSamplePositions4x[4][2] = { @@ -148,6 +169,7 @@ bool IsPixelShaderNeededWithRasterization(const Shader& shader, void GetHostViewportInfo(const RegisterFile& regs, uint32_t resolution_scale_x, uint32_t resolution_scale_y, bool origin_bottom_left, uint32_t x_max, uint32_t y_max, bool allow_reverse_z, + reg::RB_DEPTHCONTROL normalized_depth_control, bool convert_z_to_float24, bool full_float24_in_0_to_1, bool pixel_shader_writes_depth, ViewportInfo& viewport_info_out) { @@ -497,7 +519,7 @@ void GetHostViewportInfo(const RegisterFile& regs, uint32_t resolution_scale_x, } } - if (GetDepthControlForCurrentEdramMode(regs).z_enable && + if (normalized_depth_control.z_enable && regs.Get().depth_format == xenos::DepthRenderTargetFormat::kD24FS8) { if (convert_z_to_float24) { diff --git a/src/xenia/gpu/draw_util.h b/src/xenia/gpu/draw_util.h index d26ce8a6d..d5675afe2 100644 --- a/src/xenia/gpu/draw_util.h +++ b/src/xenia/gpu/draw_util.h @@ -84,18 +84,7 @@ bool IsRasterizationPotentiallyDone(const RegisterFile& regs, extern const int8_t kD3D10StandardSamplePositions2x[2][2]; extern const int8_t kD3D10StandardSamplePositions4x[4][2]; -inline reg::RB_DEPTHCONTROL GetDepthControlForCurrentEdramMode( - const RegisterFile& regs) { - xenos::ModeControl edram_mode = regs.Get().edram_mode; - if (edram_mode != xenos::ModeControl::kColorDepth && - edram_mode != xenos::ModeControl::kDepth) { - // Both depth and stencil disabled (EDRAM depth and stencil ignored). - reg::RB_DEPTHCONTROL disabled; - disabled.value = 0; - return disabled; - } - return regs.Get(); -} +reg::RB_DEPTHCONTROL GetNormalizedDepthControl(const RegisterFile& regs); constexpr float GetD3D10PolygonOffsetFactor( xenos::DepthRenderTargetFormat depth_format, bool float24_as_0_to_0_5) { @@ -183,6 +172,7 @@ struct ViewportInfo { void GetHostViewportInfo(const RegisterFile& regs, uint32_t resolution_scale_x, uint32_t resolution_scale_y, bool origin_bottom_left, uint32_t x_max, uint32_t y_max, bool allow_reverse_z, + reg::RB_DEPTHCONTROL normalized_depth_control, bool convert_z_to_float24, bool full_float24_in_0_to_1, bool pixel_shader_writes_depth, ViewportInfo& viewport_info_out); diff --git a/src/xenia/gpu/render_target_cache.cc b/src/xenia/gpu/render_target_cache.cc index d7b3c754a..d840a3550 100644 --- a/src/xenia/gpu/render_target_cache.cc +++ b/src/xenia/gpu/render_target_cache.cc @@ -2,7 +2,7 @@ ****************************************************************************** * Xenia : Xbox 360 Emulator Research Project * ****************************************************************************** - * Copyright 2021 Ben Vanik. All rights reserved. * + * Copyright 2022 Ben Vanik. All rights reserved. * * Released under the BSD license - see LICENSE in the root for more details. * ****************************************************************************** */ @@ -366,6 +366,7 @@ void RenderTargetCache::ClearCache() { void RenderTargetCache::BeginFrame() { ResetAccumulatedRenderTargets(); } bool RenderTargetCache::Update(bool is_rasterization_done, + reg::RB_DEPTHCONTROL normalized_depth_control, uint32_t normalized_color_mask) { const RegisterFile& regs = register_file(); bool interlock_barrier_only = GetPath() == Path::kPixelShaderInterlock; @@ -429,8 +430,8 @@ bool RenderTargetCache::Update(bool is_rasterization_done, uint32_t rts_are_64bpp = 0; uint32_t color_rts_are_gamma = 0; if (is_rasterization_done) { - auto rb_depthcontrol = draw_util::GetDepthControlForCurrentEdramMode(regs); - if (rb_depthcontrol.z_enable || rb_depthcontrol.stencil_enable) { + if (normalized_depth_control.z_enable || + normalized_depth_control.stencil_enable) { depth_and_color_rts_used_bits |= 1; auto rb_depth_info = regs.Get(); // std::min for safety, to avoid negative numbers in case it's completely diff --git a/src/xenia/gpu/render_target_cache.h b/src/xenia/gpu/render_target_cache.h index f0e59fb5f..2a04df75a 100644 --- a/src/xenia/gpu/render_target_cache.h +++ b/src/xenia/gpu/render_target_cache.h @@ -2,7 +2,7 @@ ****************************************************************************** * Xenia : Xbox 360 Emulator Research Project * ****************************************************************************** - * Copyright 2021 Ben Vanik. All rights reserved. * + * Copyright 2022 Ben Vanik. All rights reserved. * * Released under the BSD license - see LICENSE in the root for more details. * ****************************************************************************** */ @@ -23,6 +23,7 @@ #include "xenia/base/cvar.h" #include "xenia/gpu/draw_util.h" #include "xenia/gpu/register_file.h" +#include "xenia/gpu/registers.h" #include "xenia/gpu/xenos.h" DECLARE_bool(depth_transfer_not_equal_test); @@ -215,6 +216,7 @@ class RenderTargetCache { virtual void BeginFrame(); virtual bool Update(bool is_rasterization_done, + reg::RB_DEPTHCONTROL normalized_depth_control, uint32_t normalized_color_mask); // Returns bits where 0 is whether a depth render target is currently bound on