CR0 tests for addc, addic.

src/xenia/cpu/frontend/test/instr_addc.s

@@ -107,3 +107,160 @@ test_addc_5_constant:
   #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
   #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
   #_ REGISTER_OUT r6 1
+
+test_addc_cr_1:
+  #_ REGISTER_IN r4 1
+  #_ REGISTER_IN r5 2
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 3
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addc_cr_1_constant:
+  li r4, 1
+  li r5, 2
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 3
+  #_ REGISTER_OUT r4 1
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addc_cr_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x80000000
+
+test_addc_cr_2_constant:
+  li r4, -1
+  li r5, 0
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x80000000
+
+test_addc_cr_3:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 1
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x20000000
+
+test_addc_cr_3_constant:
+  li r4, -1
+  li r5, 1
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x20000000
+
+test_addc_cr_4:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 123
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x000000000000007A
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 123
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addc_cr_4_constant:
+  li r4, -1
+  li r5, 123
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x000000000000007A
+  #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 123
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addc_cr_5:
+  #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x80000000
+
+test_addc_cr_5_constant:
+  li r5, -1
+  srdi r4, r5, 1
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x7FFFFFFFFFFFFFFE
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x80000000
+
+test_addc_cr_6:
+  #_ REGISTER_IN r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_IN r5 2
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000001
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addc_cr_6_constant:
+  li r4, -1
+  srdi r4, r4, 1
+  li r5, 2
+  addc. r3, r4, r5
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r3 0x8000000000000001
+  #_ REGISTER_OUT r4 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r5 2
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000

src/xenia/cpu/frontend/test/instr_addic.s

@@ -29,3 +29,43 @@ test_addic_2_constant:
   blr
   #_ REGISTER_OUT r4 0
   #_ REGISTER_OUT r6 1
+
+test_addic_cr_1:
+  #_ REGISTER_IN r4 1
+  addic. r4, r4, 1
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addic_cr_1_constant:
+  li r4, 1
+  addic. r4, r4, 1
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r4 2
+  #_ REGISTER_OUT r6 0
+  #_ REGISTER_OUT r12 0x40000000
+
+test_addic_cr_2:
+  #_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
+  addic. r4, r4, 1
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x20000000
+
+test_addic_cr_2_constant:
+  li r4, -1
+  addic. r4, r4, 1
+  adde r6, r0, r0
+  mfcr r12
+  blr
+  #_ REGISTER_OUT r4 0
+  #_ REGISTER_OUT r6 1
+  #_ REGISTER_OUT r12 0x20000000