diff --git a/src/xenia/cpu/frontend/test/bin/instr_addme.bin b/src/xenia/cpu/frontend/test/bin/instr_addme.bin index c47a75603..d89bee67a 100644 Binary files a/src/xenia/cpu/frontend/test/bin/instr_addme.bin and b/src/xenia/cpu/frontend/test/bin/instr_addme.bin differ diff --git a/src/xenia/cpu/frontend/test/bin/instr_addme.dis b/src/xenia/cpu/frontend/test/bin/instr_addme.dis index c46af7f75..ee07c5821 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_addme.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_addme.dis @@ -5,49 +5,109 @@ Disassembly of section .text: 100004: 7c c0 01 14 adde r6,r0,r0 100008: 4e 80 00 20 blr -000000000010000c : - 10000c: 7c 63 1a 78 xor r3,r3,r3 - 100010: 7c 63 18 f8 not r3,r3 - 100014: 30 63 00 01 addic r3,r3,1 - 100018: 7c 64 01 d4 addme r3,r4 - 10001c: 7c c0 01 14 adde r6,r0,r0 - 100020: 4e 80 00 20 blr +000000000010000c : + 10000c: 38 80 00 01 li r4,1 + 100010: 7c 64 01 d4 addme r3,r4 + 100014: 7c c0 01 14 adde r6,r0,r0 + 100018: 4e 80 00 20 blr -0000000000100024 : - 100024: 7c 64 01 d4 addme r3,r4 - 100028: 7c c0 01 14 adde r6,r0,r0 - 10002c: 4e 80 00 20 blr +000000000010001c : + 10001c: 7c 63 1a 78 xor r3,r3,r3 + 100020: 7c 63 18 f8 not r3,r3 + 100024: 30 63 00 01 addic r3,r3,1 + 100028: 7c 64 01 d4 addme r3,r4 + 10002c: 7c c0 01 14 adde r6,r0,r0 + 100030: 4e 80 00 20 blr -0000000000100030 : - 100030: 7c 63 1a 78 xor r3,r3,r3 - 100034: 7c 63 18 f8 not r3,r3 - 100038: 30 63 00 01 addic r3,r3,1 - 10003c: 7c 64 01 d4 addme r3,r4 - 100040: 7c c0 01 14 adde r6,r0,r0 - 100044: 4e 80 00 20 blr +0000000000100034 : + 100034: 38 80 00 01 li r4,1 + 100038: 7c 63 1a 78 xor r3,r3,r3 + 10003c: 7c 63 18 f8 not r3,r3 + 100040: 30 63 00 01 addic r3,r3,1 + 100044: 7c 64 01 d4 addme r3,r4 + 100048: 7c c0 01 14 adde r6,r0,r0 + 10004c: 4e 80 00 20 blr -0000000000100048 : - 100048: 7c 64 01 d4 addme r3,r4 - 10004c: 7c c0 01 14 adde r6,r0,r0 - 100050: 4e 80 00 20 blr +0000000000100050 : + 100050: 7c 64 01 d4 addme r3,r4 + 100054: 7c c0 01 14 adde r6,r0,r0 + 100058: 4e 80 00 20 blr -0000000000100054 : - 100054: 7c 63 1a 78 xor r3,r3,r3 - 100058: 7c 63 18 f8 not r3,r3 - 10005c: 30 63 00 01 addic r3,r3,1 +000000000010005c : + 10005c: 38 80 00 0c li r4,12 100060: 7c 64 01 d4 addme r3,r4 100064: 7c c0 01 14 adde r6,r0,r0 100068: 4e 80 00 20 blr -000000000010006c : - 10006c: 7c 64 01 d4 addme r3,r4 - 100070: 7c c0 01 14 adde r6,r0,r0 - 100074: 4e 80 00 20 blr +000000000010006c : + 10006c: 7c 63 1a 78 xor r3,r3,r3 + 100070: 7c 63 18 f8 not r3,r3 + 100074: 30 63 00 01 addic r3,r3,1 + 100078: 7c 64 01 d4 addme r3,r4 + 10007c: 7c c0 01 14 adde r6,r0,r0 + 100080: 4e 80 00 20 blr -0000000000100078 : - 100078: 7c 63 1a 78 xor r3,r3,r3 - 10007c: 7c 63 18 f8 not r3,r3 - 100080: 30 63 00 01 addic r3,r3,1 - 100084: 7c 64 01 d4 addme r3,r4 - 100088: 7c c0 01 14 adde r6,r0,r0 - 10008c: 4e 80 00 20 blr +0000000000100084 : + 100084: 38 80 00 0c li r4,12 + 100088: 7c 63 1a 78 xor r3,r3,r3 + 10008c: 7c 63 18 f8 not r3,r3 + 100090: 30 63 00 01 addic r3,r3,1 + 100094: 7c 64 01 d4 addme r3,r4 + 100098: 7c c0 01 14 adde r6,r0,r0 + 10009c: 4e 80 00 20 blr + +00000000001000a0 : + 1000a0: 7c 64 01 d4 addme r3,r4 + 1000a4: 7c c0 01 14 adde r6,r0,r0 + 1000a8: 4e 80 00 20 blr + +00000000001000ac : + 1000ac: 38 80 ff ff li r4,-1 + 1000b0: 7c 64 01 d4 addme r3,r4 + 1000b4: 7c c0 01 14 adde r6,r0,r0 + 1000b8: 4e 80 00 20 blr + +00000000001000bc : + 1000bc: 7c 63 1a 78 xor r3,r3,r3 + 1000c0: 7c 63 18 f8 not r3,r3 + 1000c4: 30 63 00 01 addic r3,r3,1 + 1000c8: 7c 64 01 d4 addme r3,r4 + 1000cc: 7c c0 01 14 adde r6,r0,r0 + 1000d0: 4e 80 00 20 blr + +00000000001000d4 : + 1000d4: 38 80 ff ff li r4,-1 + 1000d8: 7c 63 1a 78 xor r3,r3,r3 + 1000dc: 7c 63 18 f8 not r3,r3 + 1000e0: 30 63 00 01 addic r3,r3,1 + 1000e4: 7c 64 01 d4 addme r3,r4 + 1000e8: 7c c0 01 14 adde r6,r0,r0 + 1000ec: 4e 80 00 20 blr + +00000000001000f0 : + 1000f0: 7c 64 01 d4 addme r3,r4 + 1000f4: 7c c0 01 14 adde r6,r0,r0 + 1000f8: 4e 80 00 20 blr + +00000000001000fc : + 1000fc: 38 80 00 00 li r4,0 + 100100: 7c 64 01 d4 addme r3,r4 + 100104: 7c c0 01 14 adde r6,r0,r0 + 100108: 4e 80 00 20 blr + +000000000010010c : + 10010c: 7c 63 1a 78 xor r3,r3,r3 + 100110: 7c 63 18 f8 not r3,r3 + 100114: 30 63 00 01 addic r3,r3,1 + 100118: 7c 64 01 d4 addme r3,r4 + 10011c: 7c c0 01 14 adde r6,r0,r0 + 100120: 4e 80 00 20 blr + +0000000000100124 : + 100124: 38 80 00 00 li r4,0 + 100128: 7c 63 1a 78 xor r3,r3,r3 + 10012c: 7c 63 18 f8 not r3,r3 + 100130: 30 63 00 01 addic r3,r3,1 + 100134: 7c 64 01 d4 addme r3,r4 + 100138: 7c c0 01 14 adde r6,r0,r0 + 10013c: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_addme.map b/src/xenia/cpu/frontend/test/bin/instr_addme.map index 1f9efa1b4..dbc64cb90 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_addme.map +++ b/src/xenia/cpu/frontend/test/bin/instr_addme.map @@ -1,8 +1,16 @@ 0000000000000000 t test_addme_1 -000000000000000c t test_addme_2 -0000000000000024 t test_addme_3 -0000000000000030 t test_addme_4 -0000000000000048 t test_addme_5 -0000000000000054 t test_addme_6 -000000000000006c t test_addme_7 -0000000000000078 t test_addme_8 +000000000000000c t test_addme_1_constant +000000000000001c t test_addme_2 +0000000000000034 t test_addme_2_constant +0000000000000050 t test_addme_3 +000000000000005c t test_addme_3_constant +000000000000006c t test_addme_4 +0000000000000084 t test_addme_4_constant +00000000000000a0 t test_addme_5 +00000000000000ac t test_addme_5_constant +00000000000000bc t test_addme_6 +00000000000000d4 t test_addme_6_constant +00000000000000f0 t test_addme_7 +00000000000000fc t test_addme_7_constant +000000000000010c t test_addme_8 +0000000000000124 t test_addme_8_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_addze.bin b/src/xenia/cpu/frontend/test/bin/instr_addze.bin index 34b5d022a..da738d2d6 100644 Binary files a/src/xenia/cpu/frontend/test/bin/instr_addze.bin and b/src/xenia/cpu/frontend/test/bin/instr_addze.bin differ diff --git a/src/xenia/cpu/frontend/test/bin/instr_addze.dis b/src/xenia/cpu/frontend/test/bin/instr_addze.dis index cb537e390..40472a41d 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_addze.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_addze.dis @@ -5,49 +5,109 @@ Disassembly of section .text: 100004: 7c c0 01 14 adde r6,r0,r0 100008: 4e 80 00 20 blr -000000000010000c : - 10000c: 7c 63 1a 78 xor r3,r3,r3 - 100010: 7c 63 18 f8 not r3,r3 - 100014: 30 63 00 01 addic r3,r3,1 - 100018: 7c 64 01 94 addze r3,r4 - 10001c: 7c c0 01 14 adde r6,r0,r0 - 100020: 4e 80 00 20 blr +000000000010000c : + 10000c: 38 80 00 01 li r4,1 + 100010: 7c 64 01 94 addze r3,r4 + 100014: 7c c0 01 14 adde r6,r0,r0 + 100018: 4e 80 00 20 blr -0000000000100024 : - 100024: 7c 64 01 94 addze r3,r4 - 100028: 7c c0 01 14 adde r6,r0,r0 - 10002c: 4e 80 00 20 blr +000000000010001c : + 10001c: 7c 63 1a 78 xor r3,r3,r3 + 100020: 7c 63 18 f8 not r3,r3 + 100024: 30 63 00 01 addic r3,r3,1 + 100028: 7c 64 01 94 addze r3,r4 + 10002c: 7c c0 01 14 adde r6,r0,r0 + 100030: 4e 80 00 20 blr -0000000000100030 : - 100030: 7c 63 1a 78 xor r3,r3,r3 - 100034: 7c 63 18 f8 not r3,r3 - 100038: 30 63 00 01 addic r3,r3,1 - 10003c: 7c 64 01 94 addze r3,r4 - 100040: 7c c0 01 14 adde r6,r0,r0 - 100044: 4e 80 00 20 blr +0000000000100034 : + 100034: 38 80 00 01 li r4,1 + 100038: 7c 63 1a 78 xor r3,r3,r3 + 10003c: 7c 63 18 f8 not r3,r3 + 100040: 30 63 00 01 addic r3,r3,1 + 100044: 7c 64 01 94 addze r3,r4 + 100048: 7c c0 01 14 adde r6,r0,r0 + 10004c: 4e 80 00 20 blr -0000000000100048 : - 100048: 7c 64 01 94 addze r3,r4 - 10004c: 7c c0 01 14 adde r6,r0,r0 - 100050: 4e 80 00 20 blr +0000000000100050 : + 100050: 7c 64 01 94 addze r3,r4 + 100054: 7c c0 01 14 adde r6,r0,r0 + 100058: 4e 80 00 20 blr -0000000000100054 : - 100054: 7c 63 1a 78 xor r3,r3,r3 - 100058: 7c 63 18 f8 not r3,r3 - 10005c: 30 63 00 01 addic r3,r3,1 +000000000010005c : + 10005c: 38 80 00 0c li r4,12 100060: 7c 64 01 94 addze r3,r4 100064: 7c c0 01 14 adde r6,r0,r0 100068: 4e 80 00 20 blr -000000000010006c : - 10006c: 7c 64 01 94 addze r3,r4 - 100070: 7c c0 01 14 adde r6,r0,r0 - 100074: 4e 80 00 20 blr +000000000010006c : + 10006c: 7c 63 1a 78 xor r3,r3,r3 + 100070: 7c 63 18 f8 not r3,r3 + 100074: 30 63 00 01 addic r3,r3,1 + 100078: 7c 64 01 94 addze r3,r4 + 10007c: 7c c0 01 14 adde r6,r0,r0 + 100080: 4e 80 00 20 blr -0000000000100078 : - 100078: 7c 63 1a 78 xor r3,r3,r3 - 10007c: 7c 63 18 f8 not r3,r3 - 100080: 30 63 00 01 addic r3,r3,1 - 100084: 7c 64 01 94 addze r3,r4 - 100088: 7c c0 01 14 adde r6,r0,r0 - 10008c: 4e 80 00 20 blr +0000000000100084 : + 100084: 38 80 00 0c li r4,12 + 100088: 7c 63 1a 78 xor r3,r3,r3 + 10008c: 7c 63 18 f8 not r3,r3 + 100090: 30 63 00 01 addic r3,r3,1 + 100094: 7c 64 01 94 addze r3,r4 + 100098: 7c c0 01 14 adde r6,r0,r0 + 10009c: 4e 80 00 20 blr + +00000000001000a0 : + 1000a0: 7c 64 01 94 addze r3,r4 + 1000a4: 7c c0 01 14 adde r6,r0,r0 + 1000a8: 4e 80 00 20 blr + +00000000001000ac : + 1000ac: 38 80 ff ff li r4,-1 + 1000b0: 7c 64 01 94 addze r3,r4 + 1000b4: 7c c0 01 14 adde r6,r0,r0 + 1000b8: 4e 80 00 20 blr + +00000000001000bc : + 1000bc: 7c 63 1a 78 xor r3,r3,r3 + 1000c0: 7c 63 18 f8 not r3,r3 + 1000c4: 30 63 00 01 addic r3,r3,1 + 1000c8: 7c 64 01 94 addze r3,r4 + 1000cc: 7c c0 01 14 adde r6,r0,r0 + 1000d0: 4e 80 00 20 blr + +00000000001000d4 : + 1000d4: 38 80 ff ff li r4,-1 + 1000d8: 7c 63 1a 78 xor r3,r3,r3 + 1000dc: 7c 63 18 f8 not r3,r3 + 1000e0: 30 63 00 01 addic r3,r3,1 + 1000e4: 7c 64 01 94 addze r3,r4 + 1000e8: 7c c0 01 14 adde r6,r0,r0 + 1000ec: 4e 80 00 20 blr + +00000000001000f0 : + 1000f0: 7c 64 01 94 addze r3,r4 + 1000f4: 7c c0 01 14 adde r6,r0,r0 + 1000f8: 4e 80 00 20 blr + +00000000001000fc : + 1000fc: 38 80 00 00 li r4,0 + 100100: 7c 64 01 94 addze r3,r4 + 100104: 7c c0 01 14 adde r6,r0,r0 + 100108: 4e 80 00 20 blr + +000000000010010c : + 10010c: 7c 63 1a 78 xor r3,r3,r3 + 100110: 7c 63 18 f8 not r3,r3 + 100114: 30 63 00 01 addic r3,r3,1 + 100118: 7c 64 01 94 addze r3,r4 + 10011c: 7c c0 01 14 adde r6,r0,r0 + 100120: 4e 80 00 20 blr + +0000000000100124 : + 100124: 38 80 00 00 li r4,0 + 100128: 7c 63 1a 78 xor r3,r3,r3 + 10012c: 7c 63 18 f8 not r3,r3 + 100130: 30 63 00 01 addic r3,r3,1 + 100134: 7c 64 01 94 addze r3,r4 + 100138: 7c c0 01 14 adde r6,r0,r0 + 10013c: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_addze.map b/src/xenia/cpu/frontend/test/bin/instr_addze.map index 99bf605c6..8c4cc6597 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_addze.map +++ b/src/xenia/cpu/frontend/test/bin/instr_addze.map @@ -1,8 +1,16 @@ 0000000000000000 t test_addze_1 -000000000000000c t test_addze_2 -0000000000000024 t test_addze_3 -0000000000000030 t test_addze_4 -0000000000000048 t test_addze_5 -0000000000000054 t test_addze_6 -000000000000006c t test_addze_7 -0000000000000078 t test_addze_8 +000000000000000c t test_addze_1_constant +000000000000001c t test_addze_2 +0000000000000034 t test_addze_2_constant +0000000000000050 t test_addze_3 +000000000000005c t test_addze_3_constant +000000000000006c t test_addze_4 +0000000000000084 t test_addze_4_constant +00000000000000a0 t test_addze_5 +00000000000000ac t test_addze_5_constant +00000000000000bc t test_addze_6 +00000000000000d4 t test_addze_6_constant +00000000000000f0 t test_addze_7 +00000000000000fc t test_addze_7_constant +000000000000010c t test_addze_8 +0000000000000124 t test_addze_8_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_divd.bin b/src/xenia/cpu/frontend/test/bin/instr_divd.bin index 9c4af8913..bbd24d2bd 100644 Binary files a/src/xenia/cpu/frontend/test/bin/instr_divd.bin and b/src/xenia/cpu/frontend/test/bin/instr_divd.bin differ diff --git a/src/xenia/cpu/frontend/test/bin/instr_divd.dis b/src/xenia/cpu/frontend/test/bin/instr_divd.dis index b52369a49..3bb4bc33a 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_divd.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_divd.dis @@ -4,26 +4,68 @@ Disassembly of section .text: 100000: 7c 64 2b d2 divd r3,r4,r5 100004: 4e 80 00 20 blr -0000000000100008 : - 100008: 7c 64 2b d2 divd r3,r4,r5 - 10000c: 4e 80 00 20 blr - -0000000000100010 : +0000000000100008 : + 100008: 38 80 00 01 li r4,1 + 10000c: 38 a0 00 02 li r5,2 100010: 7c 64 2b d2 divd r3,r4,r5 100014: 4e 80 00 20 blr -0000000000100018 : +0000000000100018 : 100018: 7c 64 2b d2 divd r3,r4,r5 10001c: 4e 80 00 20 blr -0000000000100020 : - 100020: 7c 64 2b d2 divd r3,r4,r5 - 100024: 4e 80 00 20 blr - -0000000000100028 : +0000000000100020 : + 100020: 38 80 00 02 li r4,2 + 100024: 38 a0 00 01 li r5,1 100028: 7c 64 2b d2 divd r3,r4,r5 10002c: 4e 80 00 20 blr -0000000000100030 : +0000000000100030 : 100030: 7c 64 2b d2 divd r3,r4,r5 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 38 80 00 23 li r4,35 + 10003c: 38 a0 00 07 li r5,7 + 100040: 7c 64 2b d2 divd r3,r4,r5 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c 64 2b d2 divd r3,r4,r5 + 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 38 80 00 00 li r4,0 + 100054: 38 a0 00 01 li r5,1 + 100058: 7c 64 2b d2 divd r3,r4,r5 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 7c 64 2b d2 divd r3,r4,r5 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 38 80 ff ff li r4,-1 + 10006c: 38 a0 00 01 li r5,1 + 100070: 7c 64 2b d2 divd r3,r4,r5 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 7c 64 2b d2 divd r3,r4,r5 + 10007c: 4e 80 00 20 blr + +0000000000100080 : + 100080: 38 80 ff ff li r4,-1 + 100084: 38 a0 ff ff li r5,-1 + 100088: 7c 64 2b d2 divd r3,r4,r5 + 10008c: 4e 80 00 20 blr + +0000000000100090 : + 100090: 7c 64 2b d2 divd r3,r4,r5 + 100094: 4e 80 00 20 blr + +0000000000100098 : + 100098: 38 80 00 01 li r4,1 + 10009c: 38 a0 ff ff li r5,-1 + 1000a0: 7c 64 2b d2 divd r3,r4,r5 + 1000a4: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_divd.map b/src/xenia/cpu/frontend/test/bin/instr_divd.map index a5ade4aad..c66ff9053 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_divd.map +++ b/src/xenia/cpu/frontend/test/bin/instr_divd.map @@ -1,7 +1,14 @@ 0000000000000000 t test_divd_1 -0000000000000008 t test_divd_3 -0000000000000010 t test_divd_4 -0000000000000018 t test_divd_5 -0000000000000020 t test_divd_6 -0000000000000028 t test_divd_7 -0000000000000030 t test_divd_8 +0000000000000008 t test_divd_1_constant +0000000000000018 t test_divd_3 +0000000000000020 t test_divd_3_constant +0000000000000030 t test_divd_4 +0000000000000038 t test_divd_4_constant +0000000000000048 t test_divd_5 +0000000000000050 t test_divd_5_constant +0000000000000060 t test_divd_6 +0000000000000068 t test_divd_6_constant +0000000000000078 t test_divd_7 +0000000000000080 t test_divd_7_constant +0000000000000090 t test_divd_8 +0000000000000098 t test_divd_8_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_divdu.bin b/src/xenia/cpu/frontend/test/bin/instr_divdu.bin index a44adc4b8..f82c79444 100644 Binary files a/src/xenia/cpu/frontend/test/bin/instr_divdu.bin and b/src/xenia/cpu/frontend/test/bin/instr_divdu.bin differ diff --git a/src/xenia/cpu/frontend/test/bin/instr_divdu.dis b/src/xenia/cpu/frontend/test/bin/instr_divdu.dis index e9e34f334..14b5ba8de 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_divdu.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_divdu.dis @@ -4,30 +4,79 @@ Disassembly of section .text: 100000: 7c 64 2b 92 divdu r3,r4,r5 100004: 4e 80 00 20 blr -0000000000100008 : - 100008: 7c 64 2b 92 divdu r3,r4,r5 - 10000c: 4e 80 00 20 blr - -0000000000100010 : +0000000000100008 : + 100008: 38 80 00 01 li r4,1 + 10000c: 38 a0 00 02 li r5,2 100010: 7c 64 2b 92 divdu r3,r4,r5 100014: 4e 80 00 20 blr -0000000000100018 : +0000000000100018 : 100018: 7c 64 2b 92 divdu r3,r4,r5 10001c: 4e 80 00 20 blr -0000000000100020 : - 100020: 7c 64 2b 92 divdu r3,r4,r5 - 100024: 4e 80 00 20 blr - -0000000000100028 : +0000000000100020 : + 100020: 38 80 00 02 li r4,2 + 100024: 38 a0 00 01 li r5,1 100028: 7c 64 2b 92 divdu r3,r4,r5 10002c: 4e 80 00 20 blr -0000000000100030 : +0000000000100030 : 100030: 7c 64 2b 92 divdu r3,r4,r5 100034: 4e 80 00 20 blr -0000000000100038 : - 100038: 7c 64 2b 92 divdu r3,r4,r5 - 10003c: 4e 80 00 20 blr +0000000000100038 : + 100038: 38 80 00 23 li r4,35 + 10003c: 38 a0 00 07 li r5,7 + 100040: 7c 64 2b 92 divdu r3,r4,r5 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c 64 2b 92 divdu r3,r4,r5 + 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 38 80 00 00 li r4,0 + 100054: 38 a0 00 01 li r5,1 + 100058: 7c 64 2b 92 divdu r3,r4,r5 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 7c 64 2b 92 divdu r3,r4,r5 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 38 80 ff ff li r4,-1 + 10006c: 38 a0 00 01 li r5,1 + 100070: 7c 64 2b 92 divdu r3,r4,r5 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 7c 64 2b 92 divdu r3,r4,r5 + 10007c: 4e 80 00 20 blr + +0000000000100080 : + 100080: 38 80 ff ff li r4,-1 + 100084: 38 a0 ff ff li r5,-1 + 100088: 7c 64 2b 92 divdu r3,r4,r5 + 10008c: 4e 80 00 20 blr + +0000000000100090 : + 100090: 7c 64 2b 92 divdu r3,r4,r5 + 100094: 4e 80 00 20 blr + +0000000000100098 : + 100098: 38 80 00 01 li r4,1 + 10009c: 38 a0 ff ff li r5,-1 + 1000a0: 7c 64 2b 92 divdu r3,r4,r5 + 1000a4: 4e 80 00 20 blr + +00000000001000a8 : + 1000a8: 7c 64 2b 92 divdu r3,r4,r5 + 1000ac: 4e 80 00 20 blr + +00000000001000b0 : + 1000b0: 38 80 00 01 li r4,1 + 1000b4: 78 84 f8 06 rldicr r4,r4,63,0 + 1000b8: 38 a0 ff ff li r5,-1 + 1000bc: 7c 64 2b 92 divdu r3,r4,r5 + 1000c0: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_divdu.map b/src/xenia/cpu/frontend/test/bin/instr_divdu.map index 5d6d73889..38ae2481e 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_divdu.map +++ b/src/xenia/cpu/frontend/test/bin/instr_divdu.map @@ -1,8 +1,16 @@ 0000000000000000 t test_divdu_1 -0000000000000008 t test_divdu_3 -0000000000000010 t test_divdu_4 -0000000000000018 t test_divdu_5 -0000000000000020 t test_divdu_6 -0000000000000028 t test_divdu_7 -0000000000000030 t test_divdu_8 -0000000000000038 t test_divdu_9 +0000000000000008 t test_divdu_1_constant +0000000000000018 t test_divdu_3 +0000000000000020 t test_divdu_3_constant +0000000000000030 t test_divdu_4 +0000000000000038 t test_divdu_4_constant +0000000000000048 t test_divdu_5 +0000000000000050 t test_divdu_5_constant +0000000000000060 t test_divdu_6 +0000000000000068 t test_divdu_6_constant +0000000000000078 t test_divdu_7 +0000000000000080 t test_divdu_7_constant +0000000000000090 t test_divdu_8 +0000000000000098 t test_divdu_8_constant +00000000000000a8 t test_divdu_9 +00000000000000b0 t test_divdu_9_constant diff --git a/src/xenia/cpu/frontend/test/instr_divdu.s b/src/xenia/cpu/frontend/test/instr_divdu.s index cd073859c..be08b67a1 100644 --- a/src/xenia/cpu/frontend/test/instr_divdu.s +++ b/src/xenia/cpu/frontend/test/instr_divdu.s @@ -154,12 +154,12 @@ test_divdu_9: #_ REGISTER_OUT r5 -1 # TODO(benvanik): integer overflow (=0) -#test_divdu_9_constant: -# li r4, 1 -# sldi r4, r4, 63 -# li r5, -1 -# divdu r3, r4, r5 -# blr -# #_ REGISTER_OUT r3 0 -# #_ REGISTER_OUT r4 0x8000000000000000 -# #_ REGISTER_OUT r5 -1 +test_divdu_9_constant: + li r4, 1 + sldi r4, r4, 63 + li r5, -1 + divdu r3, r4, r5 + blr + #_ REGISTER_OUT r3 0 + #_ REGISTER_OUT r4 0x8000000000000000 + #_ REGISTER_OUT r5 -1 diff --git a/src/xenia/cpu/hir/value.cc b/src/xenia/cpu/hir/value.cc index 0e37cfd03..80d2f6415 100644 --- a/src/xenia/cpu/hir/value.cc +++ b/src/xenia/cpu/hir/value.cc @@ -308,16 +308,16 @@ void Value::Div(Value* other) { assert_true(type == other->type); switch (type) { case INT8_TYPE: - constant.i8 /= other->constant.i8; + constant.i8 /= uint8_t(other->constant.i8); break; case INT16_TYPE: - constant.i16 /= other->constant.i16; + constant.i16 /= uint16_t(other->constant.i16); break; case INT32_TYPE: - constant.i32 /= other->constant.i32; + constant.i32 /= uint32_t(other->constant.i32); break; case INT64_TYPE: - constant.i64 /= other->constant.i64; + constant.i64 /= uint64_t(other->constant.i64); break; case FLOAT32_TYPE: constant.f32 /= other->constant.f32;