RECIP_IEEE.
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# GPU Documentation
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## References
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### Command Buffer/Registers
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### Shaders
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* [LLVM R600 Tables](https://llvm.org/viewvc/llvm-project/llvm/trunk/lib/Target/R600/R600Instructions.td)
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** The opcode formats don't match, but the name->psuedo code is correct.
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@ -1242,6 +1242,24 @@ int TranslateALU_SETNEs(
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return TranslateALU_SETXXs(ctx, alu, "!=");
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}
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int TranslateALU_RECIP_IEEE(
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xe_gpu_translate_ctx_t& ctx, const instr_alu_t& alu) {
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AppendDestReg(ctx, alu.scalar_dest, alu.scalar_write_mask, alu.export_data);
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ctx.output->append(" = ");
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if (alu.scalar_clamp) {
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ctx.output->append("saturate(");
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}
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ctx.output->append("(1.0 / ");
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AppendSrcReg(ctx, alu.src3_reg, alu.src3_sel, alu.src3_swiz, alu.src3_reg_negate, alu.src3_reg_abs);
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ctx.output->append(")");
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if (alu.scalar_clamp) {
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ctx.output->append(")");
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}
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ctx.output->append(";\n");
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AppendDestRegPost(ctx, alu.scalar_dest, alu.scalar_write_mask, alu.export_data);
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return 0;
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}
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int TranslateALU_MUL_CONST_0(
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xe_gpu_translate_ctx_t& ctx, const instr_alu_t& alu) {
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AppendDestReg(ctx, alu.scalar_dest, alu.scalar_write_mask, alu.export_data);
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@ -1392,7 +1410,7 @@ static xe_gpu_translate_alu_info_t scalar_alu_instrs[0x40] = {
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ALU_INSTR(LOG_IEEE, 1), // 16
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ALU_INSTR(RECIP_CLAMP, 1), // 17
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ALU_INSTR(RECIP_FF, 1), // 18
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ALU_INSTR(RECIP_IEEE, 1), // 19
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ALU_INSTR_IMPL(RECIP_IEEE, 1), // 19
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ALU_INSTR(RECIPSQ_CLAMP, 1), // 20
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ALU_INSTR(RECIPSQ_FF, 1), // 21
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ALU_INSTR(RECIPSQ_IEEE, 1), // 22
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