diff --git a/src/xenia/cpu/compiler/passes/constant_propagation_pass.cc b/src/xenia/cpu/compiler/passes/constant_propagation_pass.cc index 44e1e37c1..e44fce425 100644 --- a/src/xenia/cpu/compiler/passes/constant_propagation_pass.cc +++ b/src/xenia/cpu/compiler/passes/constant_propagation_pass.cc @@ -278,11 +278,13 @@ bool ConstantPropagationPass::Run(HIRBuilder* builder) { if (i->src1.value->IsConstant()) { if (i->src1.value->type != VEC128_TYPE) { if (i->src1.value->IsConstantTrue()) { - v->set_from(i->src2.value); - i->Remove(); + auto src2 = i->src2.value; + i->Replace(&OPCODE_ASSIGN_info, 0); + i->set_src1(src2); } else if (i->src1.value->IsConstantFalse()) { - v->set_from(i->src3.value); - i->Remove(); + auto src3 = i->src3.value; + i->Replace(&OPCODE_ASSIGN_info, 0); + i->set_src1(src3); } else if (i->src2.value->IsConstant() && i->src3.value->IsConstant()) { // TODO: Select diff --git a/src/xenia/cpu/ppc/ppc_translator.cc b/src/xenia/cpu/ppc/ppc_translator.cc index 84aa47f99..ec1768163 100644 --- a/src/xenia/cpu/ppc/ppc_translator.cc +++ b/src/xenia/cpu/ppc/ppc_translator.cc @@ -53,10 +53,15 @@ PPCTranslator::PPCTranslator(PPCFrontend* frontend) : frontend_(frontend) { if (validate) compiler_->AddPass(std::make_unique()); compiler_->AddPass(std::make_unique()); if (validate) compiler_->AddPass(std::make_unique()); - compiler_->AddPass(std::make_unique()); - if (validate) compiler_->AddPass(std::make_unique()); - compiler_->AddPass(std::make_unique()); - if (validate) compiler_->AddPass(std::make_unique()); + // TODO(gibbed): loop until these passes stop making changes? + for (int i = 0; i < 5; ++i) { + compiler_->AddPass(std::make_unique()); + if (validate) + compiler_->AddPass(std::make_unique()); + compiler_->AddPass(std::make_unique()); + if (validate) + compiler_->AddPass(std::make_unique()); + } if (backend->machine_info()->supports_extended_load_store) { // Backend supports the advanced LOAD/STORE instructions. // These will save us a lot of HIR opcodes. diff --git a/src/xenia/cpu/ppc/testing/instr_slw.s b/src/xenia/cpu/ppc/testing/instr_slw.s index b1f4af3d1..e6548766a 100644 --- a/src/xenia/cpu/ppc/testing/instr_slw.s +++ b/src/xenia/cpu/ppc/testing/instr_slw.s @@ -159,3 +159,44 @@ test_slw_9_constant: #_ REGISTER_OUT r3 0 #_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF #_ REGISTER_OUT r5 32 + +test_slw_10: + #_ REGISTER_IN r4 99 + #_ REGISTER_IN r5 1 + cntlzw r5, r5 + subi r5, r5, 28 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 792 + #_ REGISTER_OUT r4 99 + #_ REGISTER_OUT r5 3 + +test_slw_10_constant: + #_ REGISTER_IN r4 99 + li r5, 1 + cntlzw r5, r5 + subi r5, r5, 28 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 792 + #_ REGISTER_OUT r4 99 + #_ REGISTER_OUT r5 3 + +test_slw_11: + #_ REGISTER_IN r4 99 + #_ REGISTER_IN r5 3 + li r5, 3 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 792 + #_ REGISTER_OUT r4 99 + #_ REGISTER_OUT r5 3 + +test_slw_11_constant: + #_ REGISTER_IN r4 99 + li r5, 3 + slw r3, r4, r5 + blr + #_ REGISTER_OUT r3 792 + #_ REGISTER_OUT r4 99 + #_ REGISTER_OUT r5 3