cntlzw tests.

src/alloy/frontend/ppc/test/bin/instr_add.dis

@@ -4,10 +4,10 @@
 
 Disassembly of section .text:
 
-0000000000100000 <test_add1>:
+0000000000100000 <test_add_1>:
   100000:	7d 65 ca 14 	add     r11,r5,r25
   100004:	4e 80 00 20 	blr
 
-0000000000100008 <test_add2>:
+0000000000100008 <test_add_2>:
   100008:	7d 60 ca 14 	add     r11,r0,r25
   10000c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_add.map

@@ -1,2 +1,2 @@
-0000000000000000 t test_add1
+0000000000000000 t test_add_1
-0000000000000008 t test_add2
+0000000000000008 t test_add_2

src/alloy/frontend/ppc/test/bin/instr_cntlzd.dis

@@ -0,0 +1,21 @@
+
+/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_cntlzd.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_cntlzd_1>:
+  100000:	7c a6 00 74 	cntlzd  r6,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_cntlzd_2>:
+  100008:	7c a6 00 74 	cntlzd  r6,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_cntlzd_3>:
+  100010:	7c a6 00 74 	cntlzd  r6,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_cntlzd_4>:
+  100018:	7c a6 00 74 	cntlzd  r6,r5
+  10001c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_cntlzd.map

@@ -0,0 +1,4 @@
+0000000000000000 t test_cntlzd_1
+0000000000000008 t test_cntlzd_2
+0000000000000010 t test_cntlzd_3
+0000000000000018 t test_cntlzd_4

src/alloy/frontend/ppc/test/bin/instr_cntlzw.dis

@@ -0,0 +1,21 @@
+
+/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_cntlzw.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_cntlzw_1>:
+  100000:	7c a6 00 34 	cntlzw  r6,r5
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_cntlzw_2>:
+  100008:	7c a6 00 34 	cntlzw  r6,r5
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_cntlzw_3>:
+  100010:	7c a6 00 34 	cntlzw  r6,r5
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_cntlzw_4>:
+  100018:	7c a6 00 34 	cntlzw  r6,r5
+  10001c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_cntlzw.map

@@ -0,0 +1,4 @@
+0000000000000000 t test_cntlzw_1
+0000000000000008 t test_cntlzw_2
+0000000000000010 t test_cntlzw_3
+0000000000000018 t test_cntlzw_4

src/alloy/frontend/ppc/test/instr_add.s

@@ -1,4 +1,4 @@
-test_add1:
+test_add_1:
   #_ REGISTER_IN r5 0x00100000
   #_ REGISTER_IN r25 0x0000FFFF
 
@@ -9,7 +9,7 @@ test_add1:
   #_ REGISTER_OUT r25 0x0000FFFF
   #_ REGISTER_OUT r11 0x0010FFFF
 
-test_add2:
+test_add_2:
   #_ REGISTER_IN r0 0x00100000
   #_ REGISTER_IN r25 0x0000FFFF
 

src/alloy/frontend/ppc/test/instr_cntlzd.s

@@ -0,0 +1,27 @@
+test_cntlzd_1:
+  #_ REGISTER_IN r5 0
+  cntlzd r6, r5
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 64
+
+test_cntlzd_2:
+  #_ REGISTER_IN r5 1
+  cntlzd r6, r5
+  blr
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 63
+
+test_cntlzd_3:
+  #_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
+  cntlzd r6, r5
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 0
+
+test_cntlzd_4:
+  #_ REGISTER_IN r5 0x7FFFFFFFFFFFFFFF
+  cntlzd r6, r5
+  blr
+  #_ REGISTER_OUT r5 0x7FFFFFFFFFFFFFFF
+  #_ REGISTER_OUT r6 1

src/alloy/frontend/ppc/test/instr_cntlzw.s

@@ -0,0 +1,27 @@
+test_cntlzw_1:
+  #_ REGISTER_IN r5 0
+  cntlzw r6, r5
+  blr
+  #_ REGISTER_OUT r5 0
+  #_ REGISTER_OUT r6 32
+
+test_cntlzw_2:
+  #_ REGISTER_IN r5 1
+  cntlzw r6, r5
+  blr
+  #_ REGISTER_OUT r5 1
+  #_ REGISTER_OUT r6 31
+
+test_cntlzw_3:
+  #_ REGISTER_IN r5 0xFFFFFFFF
+  cntlzw r6, r5
+  blr
+  #_ REGISTER_OUT r5 0xFFFFFFFF
+  #_ REGISTER_OUT r6 0
+
+test_cntlzw_4:
+  #_ REGISTER_IN r5 0x7FFFFFFF
+  cntlzw r6, r5
+  blr
+  #_ REGISTER_OUT r5 0x7FFFFFFF
+  #_ REGISTER_OUT r6 1