[GPU] Official RB name from RDNA/GCN/TeraScale/Xenos docs/news

src/xenia/gpu/registers.h

@@ -507,10 +507,15 @@ union alignas(uint32_t) PA_SC_WINDOW_SCISSOR_BR {
 static_assert_size(PA_SC_WINDOW_SCISSOR_BR, sizeof(uint32_t));
 
 /*******************************************************************************
-  ___ ___
+  ___ ___ _  _ ___  ___ ___
- | _ \ _ )
+ | _ \ __| \| |   \| __| _ \
- |   / _ \
+ |   / _|| .` | |) | _||   /
- |_|_\___/
+ |_|_\___|_|\_|___/|___|_|_\
+
+  ___   _   ___ _  _____ _  _ ___
+ | _ ) /_\ / __| |/ / __| \| |   \
+ | _ \/ _ \ (__| ' <| _|| .` | |) |
+ |___/_/ \_\___|_|\_\___|_|\_|___/
 
 *******************************************************************************/
 

src/xenia/gpu/xenos.h

@@ -194,10 +194,10 @@ enum class SurfaceNumFormat : uint32_t {
   kFloat = 7,
 };
 
-// The EDRAM is an opaque block of memory accessible by the RB pipeline stage of
+// The EDRAM is an opaque block of memory accessible by the RB (render backend)
-// the GPU, which performs output-merger functionality (color render target
+// pipeline stage of the GPU, which performs output-merger functionality (color
-// writing and blending, depth and stencil testing) and resolve (copy)
+// render target writing and blending, depth and stencil testing) and resolve
-// operations.
+// (copy) operations.
 //
 // Data in the 10 MiB of EDRAM is laid out as 2048 tiles on 80x16 32bpp MSAA
 // samples. With 2x MSAA, one pixel consists of 1x2 samples, and with 4x, it