Constant tests for divw, divwu.
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@ -7,6 +7,15 @@ test_divw_1:
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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test_divw_1_constant:
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li r4, 1
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li r5, 2
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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# TODO(benvanik): x64 ignore divide by zero (=0)
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#test_divw_2:
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# #_ REGISTER_IN r4 1
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@ -17,6 +26,16 @@ test_divw_1:
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# #_ REGISTER_OUT r4 1
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# #_ REGISTER_OUT r5 0
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# TODO(benvanik): x64 ignore divide by zero (=0)
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#test_divw_2_constant:
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# li r4, 1
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# li r5, 0
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# divw r3, r4, r5
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# blr
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# #_ REGISTER_OUT r3 0
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# #_ REGISTER_OUT r4 1
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# #_ REGISTER_OUT r5 0
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test_divw_3:
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#_ REGISTER_IN r4 2
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#_ REGISTER_IN r5 1
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@ -26,6 +45,15 @@ test_divw_3:
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#_ REGISTER_OUT r4 2
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#_ REGISTER_OUT r5 1
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test_divw_3_constant:
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li r4, 2
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li r5, 1
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 2
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#_ REGISTER_OUT r4 2
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#_ REGISTER_OUT r5 1
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test_divw_4:
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#_ REGISTER_IN r4 35
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#_ REGISTER_IN r5 7
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@ -35,6 +63,15 @@ test_divw_4:
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#_ REGISTER_OUT r4 35
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#_ REGISTER_OUT r5 7
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test_divw_4_constant:
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li r4, 35
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li r5, 7
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 5
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#_ REGISTER_OUT r4 35
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#_ REGISTER_OUT r5 7
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test_divw_5:
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#_ REGISTER_IN r4 0
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#_ REGISTER_IN r5 1
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@ -44,6 +81,15 @@ test_divw_5:
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#_ REGISTER_OUT r4 0
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#_ REGISTER_OUT r5 1
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test_divw_5_constant:
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li r4, 0
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li r5, 1
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0
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#_ REGISTER_OUT r5 1
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test_divw_6:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 1
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@ -53,6 +99,15 @@ test_divw_6:
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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test_divw_6_constant:
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li r4, -1
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li r5, 1
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x00000000FFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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test_divw_7:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
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@ -62,6 +117,15 @@ test_divw_7:
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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test_divw_7_constant:
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li r4, -1
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li r5, -1
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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test_divw_8:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
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@ -71,6 +135,15 @@ test_divw_8:
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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test_divw_8_constant:
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li r4, 1
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li r5, -1
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x00000000FFFFFFFF
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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test_divw_9:
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#_ REGISTER_IN r4 0x000000007FFFFFFF
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#_ REGISTER_IN r5 1
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@ -80,6 +153,16 @@ test_divw_9:
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#_ REGISTER_OUT r4 0x000000007FFFFFFF
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#_ REGISTER_OUT r5 1
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test_divw_9_constant:
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li r4, -1
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clrldi r4, r4, 33
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li r5, 1
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x000000007FFFFFFF
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#_ REGISTER_OUT r4 0x000000007FFFFFFF
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#_ REGISTER_OUT r5 1
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test_divw_10:
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#_ REGISTER_IN r4 0x000000007FFFFFFF
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#_ REGISTER_IN r5 0x000000007FFFFFFF
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@ -89,6 +172,16 @@ test_divw_10:
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#_ REGISTER_OUT r4 0x000000007FFFFFFF
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#_ REGISTER_OUT r5 0x000000007FFFFFFF
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test_divw_10_constant:
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li r4, -1
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clrldi r4, r4, 33
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mr r5, r4
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 0x000000007FFFFFFF
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#_ REGISTER_OUT r5 0x000000007FFFFFFF
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test_divw_11:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 0x000000007FFFFFFF
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@ -98,6 +191,16 @@ test_divw_11:
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 0x000000007FFFFFFF
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test_divw_11_constant:
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li r4, 1
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li r5, -1
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clrldi r5, r5, 33
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divw r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 0x000000007FFFFFFF
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# TODO(benvanik): integer overflow (=0)
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#test_divw_12:
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# #_ REGISTER_IN r4 0x80000000
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@ -107,3 +210,14 @@ test_divw_11:
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# #_ REGISTER_OUT r3 0
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# #_ REGISTER_OUT r4 0x80000000
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# #_ REGISTER_OUT r5 -1
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# TODO(benvanik): integer overflow (=0)
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#test_divw_12_constant:
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# li r4, 1
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# srdi r4, 31
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# li r5, -1
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# divw r3, r4, r5
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# blr
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# #_ REGISTER_OUT r3 0
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# #_ REGISTER_OUT r4 0x80000000
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# #_ REGISTER_OUT r5 -1
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@ -7,6 +7,15 @@ test_divwu_1:
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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test_divwu_1_constant:
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li r4, 1
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li r5, 2
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divwu r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 2
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# TODO(benvanik): x64 ignore divide by zero (=0)
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#test_divwu_2:
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# #_ REGISTER_IN r4 1
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@ -17,6 +26,16 @@ test_divwu_1:
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# #_ REGISTER_OUT r4 1
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# #_ REGISTER_OUT r5 0
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# TODO(benvanik): x64 ignore divide by zero (=0)
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#test_divwu_2_constant:
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# li r4, 1
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# li r5, 0
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# divwu r3, r4, r5
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# blr
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# #_ REGISTER_OUT r3 0
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# #_ REGISTER_OUT r4 1
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# #_ REGISTER_OUT r5 0
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test_divwu_3:
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#_ REGISTER_IN r4 2
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#_ REGISTER_IN r5 1
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@ -26,6 +45,15 @@ test_divwu_3:
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#_ REGISTER_OUT r4 2
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#_ REGISTER_OUT r5 1
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test_divwu_3_constant:
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li r4, 2
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li r5, 1
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divwu r3, r4, r5
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blr
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#_ REGISTER_OUT r3 2
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#_ REGISTER_OUT r4 2
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#_ REGISTER_OUT r5 1
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test_divwu_4:
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#_ REGISTER_IN r4 35
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#_ REGISTER_IN r5 7
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@ -35,6 +63,15 @@ test_divwu_4:
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#_ REGISTER_OUT r4 35
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#_ REGISTER_OUT r5 7
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test_divwu_4_constant:
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li r4, 35
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li r5, 7
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divwu r3, r4, r5
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blr
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#_ REGISTER_OUT r3 5
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#_ REGISTER_OUT r4 35
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#_ REGISTER_OUT r5 7
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test_divwu_5:
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#_ REGISTER_IN r4 0
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#_ REGISTER_IN r5 1
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@ -44,6 +81,15 @@ test_divwu_5:
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#_ REGISTER_OUT r4 0
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#_ REGISTER_OUT r5 1
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test_divwu_5_constant:
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li r4, 0
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li r5, 1
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divwu r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0
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#_ REGISTER_OUT r5 1
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test_divwu_6:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 1
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@ -53,6 +99,15 @@ test_divwu_6:
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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test_divwu_6_constant:
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li r4, -1
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li r5, 1
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divwu r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x00000000FFFFFFFF
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 1
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test_divwu_7:
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#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
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@ -62,6 +117,15 @@ test_divwu_7:
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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test_divwu_7_constant:
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li r4, -1
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li r5, -1
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divwu r3, r4, r5
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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test_divwu_8:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 0xFFFFFFFFFFFFFFFF
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@ -71,6 +135,15 @@ test_divwu_8:
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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test_divwu_8_constant:
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li r4, 1
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li r5, -1
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divwu r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 0xFFFFFFFFFFFFFFFF
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test_divwu_9:
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#_ REGISTER_IN r4 0x000000007FFFFFFF
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#_ REGISTER_IN r5 1
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@ -80,6 +153,16 @@ test_divwu_9:
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#_ REGISTER_OUT r4 0x000000007FFFFFFF
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#_ REGISTER_OUT r5 1
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test_divwu_9_constant:
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li r4, -1
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clrldi r4, r4, 33
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li r5, 1
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divwu r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0x000000007FFFFFFF
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#_ REGISTER_OUT r4 0x000000007FFFFFFF
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#_ REGISTER_OUT r5 1
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test_divwu_10:
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#_ REGISTER_IN r4 0x000000007FFFFFFF
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#_ REGISTER_IN r5 0x000000007FFFFFFF
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@ -89,6 +172,16 @@ test_divwu_10:
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#_ REGISTER_OUT r4 0x000000007FFFFFFF
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#_ REGISTER_OUT r5 0x000000007FFFFFFF
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test_divwu_10_constant:
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li r4, -1
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clrldi r4, r4, 33
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mr r5, r4
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divwu r3, r4, r5
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blr
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#_ REGISTER_OUT r3 1
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#_ REGISTER_OUT r4 0x000000007FFFFFFF
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#_ REGISTER_OUT r5 0x000000007FFFFFFF
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test_divwu_11:
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#_ REGISTER_IN r4 1
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#_ REGISTER_IN r5 0x000000007FFFFFFF
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@ -98,6 +191,16 @@ test_divwu_11:
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 0x000000007FFFFFFF
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test_divwu_11_constant:
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li r4, 1
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li r5, -1
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clrldi r5, r5, 33
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divwu r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 1
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#_ REGISTER_OUT r5 0x000000007FFFFFFF
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test_divwu_12:
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#_ REGISTER_IN r4 0x80000000
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#_ REGISTER_IN r5 -1
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@ -106,3 +209,13 @@ test_divwu_12:
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0x80000000
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#_ REGISTER_OUT r5 -1
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test_divwu_12_constant:
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li r4, 1
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sldi r4, r4, 31
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li r5, -1
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divwu r3, r4, r5
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blr
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#_ REGISTER_OUT r3 0
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#_ REGISTER_OUT r4 0x80000000
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#_ REGISTER_OUT r5 -1
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