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Removing implicit vector add/sub.

This commit is contained in:
Ben Vanik 2014-08-23 16:32:40 -07:00
parent 7ebba018ad
commit 423790209b
3 changed files with 6 additions and 44 deletions
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23
src/alloy/backend/ivm/ivm_intcode.cc
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@ -2475,21 +2475,11 @@ uint32_t IntCode_ADD_F64_F64(IntCodeState& ics, const IntCode* i) {
ics.rf[i->dest_reg].f64 = ics.rf[i->src1_reg].f64 + ics.rf[i->src2_reg].f64; ics.rf[i->dest_reg].f64 = ics.rf[i->src1_reg].f64 + ics.rf[i->src2_reg].f64;
return IA_NEXT; return IA_NEXT;
} }
uint32_t IntCode_ADD_V128_V128(IntCodeState& ics, const IntCode* i) {
assert_true(!i->flags);
const vec128_t& src1 = ics.rf[i->src1_reg].v128;
const vec128_t& src2 = ics.rf[i->src2_reg].v128;
vec128_t& dest = ics.rf[i->dest_reg].v128;
for (int n = 0; n < 4; n++) {
dest.f4[n] = src1.f4[n] + src2.f4[n];
}
return IA_NEXT;
}
int Translate_ADD(TranslationContext& ctx, Instr* i) { int Translate_ADD(TranslationContext& ctx, Instr* i) {
static IntCodeFn fns[] = { static IntCodeFn fns[] = {
IntCode_ADD_I8_I8, IntCode_ADD_I16_I16, IntCode_ADD_I32_I32, IntCode_ADD_I8_I8, IntCode_ADD_I16_I16, IntCode_ADD_I32_I32,
IntCode_ADD_I64_I64, IntCode_ADD_F32_F32, IntCode_ADD_F64_F64, IntCode_ADD_I64_I64, IntCode_ADD_F32_F32, IntCode_ADD_F64_F64,
IntCode_ADD_V128_V128, IntCode_INVALID_TYPE,
}; };
return DispatchToC(ctx, i, fns[i->dest->type]); return DispatchToC(ctx, i, fns[i->dest->type]);
} }
@ -2736,20 +2726,11 @@ uint32_t IntCode_SUB_F64_F64(IntCodeState& ics, const IntCode* i) {
ics.rf[i->dest_reg].f64 = ics.rf[i->src1_reg].f64 - ics.rf[i->src2_reg].f64; ics.rf[i->dest_reg].f64 = ics.rf[i->src1_reg].f64 - ics.rf[i->src2_reg].f64;
return IA_NEXT; return IA_NEXT;
} }
uint32_t IntCode_SUB_V128_V128(IntCodeState& ics, const IntCode* i) {
const vec128_t& src1 = ics.rf[i->src1_reg].v128;
const vec128_t& src2 = ics.rf[i->src2_reg].v128;
vec128_t& dest = ics.rf[i->dest_reg].v128;
for (int n = 0; n < 4; n++) {
dest.f4[n] = src1.f4[n] - src2.f4[n];
}
return IA_NEXT;
}
int Translate_SUB(TranslationContext& ctx, Instr* i) { int Translate_SUB(TranslationContext& ctx, Instr* i) {
static IntCodeFn fns[] = { static IntCodeFn fns[] = {
IntCode_SUB_I8_I8, IntCode_SUB_I16_I16, IntCode_SUB_I32_I32, IntCode_SUB_I8_I8, IntCode_SUB_I16_I16, IntCode_SUB_I32_I32,
IntCode_SUB_I64_I64, IntCode_SUB_F32_F32, IntCode_SUB_F64_F64, IntCode_SUB_I64_I64, IntCode_SUB_F32_F32, IntCode_SUB_F64_F64,
IntCode_SUB_V128_V128, IntCode_INVALID_TYPE,
}; };
return DispatchToC(ctx, i, fns[i->dest->type]); return DispatchToC(ctx, i, fns[i->dest->type]);
} }

23
src/alloy/backend/x64/x64_sequences.cc
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@ -2590,14 +2590,6 @@ EMITTER(ADD_F64, MATCH(I<OPCODE_ADD, F64<>, F64<>, F64<>>)) {
}); });
} }
}; };
EMITTER(ADD_V128, MATCH(I<OPCODE_ADD, V128<>, V128<>, V128<>>)) {
static void Emit(X64Emitter& e, const EmitArgType& i) {
EmitCommutativeBinaryXmmOp(e, i,
[](X64Emitter& e, Xmm dest, Xmm src1, Xmm src2) {
e.vaddps(dest, src1, src2);
});
}
};
EMITTER_OPCODE_TABLE( EMITTER_OPCODE_TABLE(
OPCODE_ADD, OPCODE_ADD,
ADD_I8, ADD_I8,
@ -2605,8 +2597,7 @@ EMITTER_OPCODE_TABLE(
ADD_I32, ADD_I32,
ADD_I64, ADD_I64,
ADD_F32, ADD_F32,
ADD_F64, ADD_F64);
ADD_V128);
// ============================================================================ // ============================================================================
@ -2847,15 +2838,6 @@ EMITTER(SUB_F64, MATCH(I<OPCODE_SUB, F64<>, F64<>, F64<>>)) {
}); });
} }
}; };
EMITTER(SUB_V128, MATCH(I<OPCODE_SUB, V128<>, V128<>, V128<>>)) {
static void Emit(X64Emitter& e, const EmitArgType& i) {
assert_true(!i.instr->flags);
EmitAssociativeBinaryXmmOp(e, i,
[](X64Emitter& e, Xmm dest, Xmm src1, Xmm src2) {
e.vsubps(dest, src1, src2);
});
}
};
EMITTER_OPCODE_TABLE( EMITTER_OPCODE_TABLE(
OPCODE_SUB, OPCODE_SUB,
SUB_I8, SUB_I8,
@ -2863,8 +2845,7 @@ EMITTER_OPCODE_TABLE(
SUB_I32, SUB_I32,
SUB_I64, SUB_I64,
SUB_F32, SUB_F32,
SUB_F64, SUB_F64);
SUB_V128);
// ============================================================================ // ============================================================================

4
src/alloy/frontend/ppc/ppc_emit_altivec.cc
View File

@ -344,7 +344,7 @@ XEEMITTER(vaddcuw, 0x10000180, VX)(PPCHIRBuilder& f, InstrData& i) {
int InstrEmit_vaddfp_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { int InstrEmit_vaddfp_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
// (VD) <- (VA) + (VB) (4 x fp) // (VD) <- (VA) + (VB) (4 x fp)
Value* v = f.Add(f.LoadVR(va), f.LoadVR(vb)); Value* v = f.VectorAdd(f.LoadVR(va), f.LoadVR(vb), FLOAT32_TYPE);
f.StoreVR(vd, v); f.StoreVR(vd, v);
return 0; return 0;
} }
@ -1568,7 +1568,7 @@ XEEMITTER(vsubcuw, 0x10000580, VX)(PPCHIRBuilder& f, InstrData& i) {
int InstrEmit_vsubfp_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) { int InstrEmit_vsubfp_(PPCHIRBuilder& f, uint32_t vd, uint32_t va, uint32_t vb) {
// (VD) <- (VA) - (VB) (4 x fp) // (VD) <- (VA) - (VB) (4 x fp)
Value* v = f.Sub(f.LoadVR(va), f.LoadVR(vb)); Value* v = f.VectorSub(f.LoadVR(va), f.LoadVR(vb), FLOAT32_TYPE);
f.StoreVR(vd, v); f.StoreVR(vd, v);
return 0; return 0;
} }