rwlinm/rlwnm tests.

src/alloy/frontend/ppc/test/bin/instr_extrwi.dis

@@ -1,9 +0,0 @@
-
-/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_extrwi.o:     file format elf64-powerpc
-
-
-Disassembly of section .text:
-
-0000000000100000 <test_extrwi>:
-  100000:	54 a7 ef 3e 	rlwinm  r7,r5,29,28,31
-  100004:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_extrwi.map

@@ -1 +0,0 @@
-0000000000000000 t test_extrwi

src/alloy/frontend/ppc/test/bin/instr_rlwinm.dis

@@ -0,0 +1,45 @@
+
+/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_rlwinm.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_rlwinm_extrwi>:
+  100000:	54 a7 ef 3e 	rlwinm  r7,r5,29,28,31
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_rlwinm_1>:
+  100008:	54 83 c2 1e 	rlwinm  r3,r4,24,8,15
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_rlwinm_2>:
+  100010:	54 83 20 36 	rlwinm  r3,r4,4,0,27
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_rlwinm_3>:
+  100018:	54 83 10 3a 	rlwinm  r3,r4,2,0,29
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_rlwinm_4>:
+  100020:	54 83 10 3b 	rlwinm. r3,r4,2,0,29
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_rlwinm_5>:
+  100028:	54 83 01 7a 	rlwinm  r3,r4,0,5,29
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_rlwinm_6>:
+  100030:	54 83 00 3e 	rotlwi  r3,r4,0
+  100034:	4e 80 00 20 	blr
+
+0000000000100038 <test_rlwinm_7>:
+  100038:	54 83 00 20 	rlwinm  r3,r4,0,0,16
+  10003c:	4e 80 00 20 	blr
+
+0000000000100040 <test_rlwinm_8>:
+  100040:	54 83 04 3e 	clrlwi  r3,r4,16
+  100044:	4e 80 00 20 	blr
+
+0000000000100048 <test_rlwinm_9>:
+  100048:	54 83 84 3e 	rlwinm  r3,r4,16,16,31
+  10004c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_rlwinm.map

@@ -0,0 +1,10 @@
+0000000000000000 t test_rlwinm_extrwi
+0000000000000008 t test_rlwinm_1
+0000000000000010 t test_rlwinm_2
+0000000000000018 t test_rlwinm_3
+0000000000000020 t test_rlwinm_4
+0000000000000028 t test_rlwinm_5
+0000000000000030 t test_rlwinm_6
+0000000000000038 t test_rlwinm_7
+0000000000000040 t test_rlwinm_8
+0000000000000048 t test_rlwinm_9

src/alloy/frontend/ppc/test/bin/instr_rlwnm.dis

@@ -0,0 +1,45 @@
+
+/cygdrive/d/dev/xenia/src/alloy/frontend/ppc/test/bin//instr_rlwnm.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_rlwnm_1>:
+  100000:	5c 83 2a 1e 	rlwnm   r3,r4,r5,8,15
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_rlwnm_2>:
+  100008:	5c 83 28 36 	rlwnm   r3,r4,r5,0,27
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_rlwnm_3>:
+  100010:	5c 83 28 3a 	rlwnm   r3,r4,r5,0,29
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_rlwnm_4>:
+  100018:	5c 83 28 3b 	rlwnm.  r3,r4,r5,0,29
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_rlwnm_5>:
+  100020:	5c 83 29 7a 	rlwnm   r3,r4,r5,5,29
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_rlwnm_6>:
+  100028:	5c 83 28 3e 	rotlw   r3,r4,r5
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_rlwnm_7>:
+  100030:	5c 83 28 20 	rlwnm   r3,r4,r5,0,16
+  100034:	4e 80 00 20 	blr
+
+0000000000100038 <test_rlwnm_8>:
+  100038:	5c 83 2c 3e 	rlwnm   r3,r4,r5,16,31
+  10003c:	4e 80 00 20 	blr
+
+0000000000100040 <test_rlwnm_9>:
+  100040:	5c 83 2c 3e 	rlwnm   r3,r4,r5,16,31
+  100044:	4e 80 00 20 	blr
+
+0000000000100048 <test_rlwnm_10>:
+  100048:	5c 83 28 3e 	rotlw   r3,r4,r5
+  10004c:	4e 80 00 20 	blr

src/alloy/frontend/ppc/test/bin/instr_rlwnm.map

@@ -0,0 +1,10 @@
+0000000000000000 t test_rlwnm_1
+0000000000000008 t test_rlwnm_2
+0000000000000010 t test_rlwnm_3
+0000000000000018 t test_rlwnm_4
+0000000000000020 t test_rlwnm_5
+0000000000000028 t test_rlwnm_6
+0000000000000030 t test_rlwnm_7
+0000000000000038 t test_rlwnm_8
+0000000000000040 t test_rlwnm_9
+0000000000000048 t test_rlwnm_10

src/alloy/frontend/ppc/test/instr_extrwi.s

@@ -1,12 +0,0 @@
-# This is a variant of rlwinmx:
-# extrwi ra,rs,n,b (n > 0) == rlwinm ra,rs,b+n,32-n,31
-
-test_extrwi:
-  #_ REGISTER_IN r5 0x30
-
-  # rlwinm r7, r5, 29, 28, 31
-  extrwi r7, r5, 4, 25
-
-  blr
-  #_ REGISTER_OUT r5 0x30
-  #_ REGISTER_OUT r7 0x06

src/alloy/frontend/ppc/test/instr_rlwinm.s

@@ -0,0 +1,72 @@
+test_rlwinm_extrwi:
+  # extrwi ra,rs,n,b (n > 0) == rlwinm ra,rs,b+n,32-n,31
+  #_ REGISTER_IN r5 0x30
+  # rlwinm r7, r5, 29, 28, 31
+  extrwi r7, r5, 4, 25
+  blr
+  #_ REGISTER_OUT r5 0x30
+  #_ REGISTER_OUT r7 0x06
+
+test_rlwinm_1:
+  #_ REGISTER_IN r4 0x12345678
+  rlwinm r3, r4, 24, 8, 15
+  blr
+  #_ REGISTER_OUT r3 0x00120000
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_2:
+  #_ REGISTER_IN r4 0x12345678
+  rlwinm r3, r4, 4, 0, 27
+  blr
+  #_ REGISTER_OUT r3 0x23456780
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_3:
+  #_ REGISTER_IN r4 0x90003000
+  rlwinm r3, r4, 2, 0, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0x4000C000
+  #_ REGISTER_OUT r4 0x90003000
+
+test_rlwinm_4:
+  #_ REGISTER_IN r4 0xB0043000
+  rlwinm. r3, r4, 2, 0, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0xC010C000
+  #_ REGISTER_OUT r4 0xB0043000
+  # CRF = 0x8
+
+test_rlwinm_5:
+  #_ REGISTER_IN r4 0x12345678
+  rlwinm r3, r4, 0, 5, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0x02345678
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_6:
+  #_ REGISTER_IN r4 0x12345678
+  rlwinm r3, r4, 0, 0, 31
+  blr
+  #_ REGISTER_OUT r3 0x12345678
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_7:
+  #_ REGISTER_IN r4 0x12345678
+  rlwinm r3, r4, 0, 0, 16
+  blr
+  #_ REGISTER_OUT r3 0x12340000
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_8:
+  #_ REGISTER_IN r4 0x12345678
+  rlwinm r3, r4, 0, 16, 31
+  blr
+  #_ REGISTER_OUT r3 0x00005678
+  #_ REGISTER_OUT r4 0x12345678
+
+test_rlwinm_9:
+  #_ REGISTER_IN r4 0x12345678
+  rlwinm r3, r4, 16, 16, 31
+  blr
+  #_ REGISTER_OUT r3 0x00001234
+  #_ REGISTER_OUT r4 0x12345678

src/alloy/frontend/ppc/test/instr_rlwnm.s

@@ -0,0 +1,90 @@
+test_rlwnm_1:
+  #_ REGISTER_IN r4 0x12345678
+  #_ REGISTER_IN r5 24
+  rlwnm r3, r4, r5, 8, 15
+  blr
+  #_ REGISTER_OUT r3 0x00120000
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 24
+
+test_rlwnm_2:
+  #_ REGISTER_IN r4 0x12345678
+  #_ REGISTER_IN r5 4
+  rlwnm r3, r4, r5, 0, 27
+  blr
+  #_ REGISTER_OUT r3 0x23456780
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 4
+
+test_rlwnm_3:
+  #_ REGISTER_IN r4 0x90003000
+  #_ REGISTER_IN r5 2
+  rlwnm r3, r4, r5, 0, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0x4000C000
+  #_ REGISTER_OUT r4 0x90003000
+  #_ REGISTER_OUT r5 2
+
+test_rlwnm_4:
+  #_ REGISTER_IN r4 0xB0043000
+  #_ REGISTER_IN r5 2
+  rlwnm. r3, r4, r5, 0, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0xC010C000
+  #_ REGISTER_OUT r4 0xB0043000
+  #_ REGISTER_OUT r5 2
+  # CRF = 0x8
+
+test_rlwnm_5:
+  #_ REGISTER_IN r4 0x12345678
+  #_ REGISTER_IN r5 0
+  rlwnm r3, r4, r5, 5, 0x1D
+  blr
+  #_ REGISTER_OUT r3 0x02345678
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 0
+
+test_rlwnm_6:
+  #_ REGISTER_IN r4 0x12345678
+  #_ REGISTER_IN r5 0
+  rlwnm r3, r4, r5, 0, 31
+  blr
+  #_ REGISTER_OUT r3 0x12345678
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 0
+
+test_rlwnm_7:
+  #_ REGISTER_IN r4 0x12345678
+  #_ REGISTER_IN r5 0
+  rlwnm r3, r4, r5, 0, 16
+  blr
+  #_ REGISTER_OUT r3 0x12340000
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 0
+
+test_rlwnm_8:
+  #_ REGISTER_IN r4 0x12345678
+  #_ REGISTER_IN r5 0
+  rlwnm r3, r4, r5, 16, 31
+  blr
+  #_ REGISTER_OUT r3 0x00005678
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 0
+
+test_rlwnm_9:
+  #_ REGISTER_IN r4 0x12345678
+  #_ REGISTER_IN r5 16
+  rlwnm r3, r4, r5, 16, 31
+  blr
+  #_ REGISTER_OUT r3 0x00001234
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 16
+
+test_rlwnm_10:
+  #_ REGISTER_IN r4 0x12345678
+  #_ REGISTER_IN r5 32
+  rlwnm r3, r4, r5, 0, 31
+  blr
+  #_ REGISTER_OUT r3 0x12345678
+  #_ REGISTER_OUT r4 0x12345678
+  #_ REGISTER_OUT r5 32