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Fixing vsl and vsr for out of range values.

This commit is contained in:
Ben Vanik 2015-08-17 07:57:15 -07:00
parent 5d61d0baa5
commit 359e5b578a
3 changed files with 18 additions and 2 deletions
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4
src/xenia/cpu/frontend/ppc_emit_altivec.cc
View File

@ -1390,7 +1390,7 @@ XEEMITTER(vsel128, VX128(5, 848), VX128)(PPCHIRBuilder& f, InstrData& i) {
XEEMITTER(vsl, 0x100001C4, VX)(PPCHIRBuilder& f, InstrData& i) {
Value* v = f.Shl(f.LoadVR(i.VX.VA),
f.And(f.Extract(f.LoadVR(i.VX.VB), 15, INT8_TYPE),
f.LoadConstantInt8(0x7F)));
f.LoadConstantInt8(0b111)));
f.StoreVR(i.VX.VD, v);
return 0;
}
@ -1573,7 +1573,7 @@ XEEMITTER(vspltisw128, VX128_3(6, 1904), VX128_3)(PPCHIRBuilder& f,
XEEMITTER(vsr, 0x100002C4, VX)(PPCHIRBuilder& f, InstrData& i) {
Value* v = f.Shr(f.LoadVR(i.VX.VA),
f.And(f.Extract(f.LoadVR(i.VX.VB), 15, INT8_TYPE),
f.LoadConstantInt8(0x7F)));
f.LoadConstantInt8(0b111)));
f.StoreVR(i.VX.VD, v);
return 0;
}

8
src/xenia/cpu/frontend/testing/instr_vsl.s
View File

@ -21,3 +21,11 @@ test_vsl_3:
blr
#_ REGISTER_OUT v3 [089119A2, 2AB33BC4, 4CD55DE6, 6EF77F80]
#_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707]
test_vsl_4:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsl v3, v3, v4
blr
#_ REGISTER_OUT v3 [089119A2, 2AB33BC4, 4CD55DE6, 6EF77F80]
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]

8
src/xenia/cpu/frontend/testing/instr_vsr.s
View File

@ -21,3 +21,11 @@ test_vsr_3:
blr
#_ REGISTER_OUT v3 [00002244, 6688AACC, EF113355, 7799BBDD]
#_ REGISTER_OUT v4 [07070707, 07070707, 07070707, 07070707]
test_vsr_4:
#_ REGISTER_IN v3 [00112233, 44556677, 8899AABB, CCDDEEFF]
#_ REGISTER_IN v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]
vsr v3, v3, v4
blr
#_ REGISTER_OUT v3 [00002244, 6688AACC, EF113355, 7799BBDD]
#_ REGISTER_OUT v4 [FFFFFFFF, FFFFFFFF, FFFFFFFF, FFFFFFFF]