ShuriZma
/
xenia-canary
mirror of https://github.com/xenia-canary/xenia-canary.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

[CPU] Add rldicx implementation 

NOTE: May or may not be correct, but works for 535507D4.
This commit is contained in:
beeanyew 2022-08-28 20:02:39 +02:00
parent 75ed343e72
commit 3569e97e0e
1 changed files with 20 additions and 2 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

22
src/xenia/cpu/ppc/ppc_emit_alu.cc
View File

@ -913,8 +913,26 @@ int InstrEmit_rldcrx(PPCHIRBuilder& f, const InstrData& i) {
} }
int InstrEmit_rldicx(PPCHIRBuilder& f, const InstrData& i) { int InstrEmit_rldicx(PPCHIRBuilder& f, const InstrData& i) {
XEINSTRNOTIMPLEMENTED(); // n <- sh[5] || sh[0:4]
return 1; // r <- ROTL64(RS, n)
// b <- mb[5] || mb[0:4]
// m <- MASK(b, ~n)
// RA <- r & m
// TODO: Check if this makes any sense. It works in 535507D4,
// but it's the only title I could find that uses this instruction.
uint32_t sh = (i.MD.SH5 << 5) | i.MD.SH;
uint32_t mb = (i.MD.MB5 << 5) | i.MD.MB;
uint64_t m = XEMASK(mb, ~sh);
Value* v = f.LoadGPR(i.MD.RT);
if (sh) {
v = f.RotateLeft(v, f.LoadConstantInt8(sh));
}
v = f.And(v, f.LoadConstantUint64(m));
f.StoreGPR(i.MD.RA, v);
if (i.MD.Rc) {
f.UpdateCR(0, v);
}
return 0;
} }
int InstrEmit_rldiclx(PPCHIRBuilder& f, const InstrData& i) { int InstrEmit_rldiclx(PPCHIRBuilder& f, const InstrData& i) {