From 32f42cd5ae597c2ba365c43f8598445f35221128 Mon Sep 17 00:00:00 2001
From: Ben Vanik <ben.vanik@gmail.com>
Date: Sun, 2 Nov 2014 17:32:50 -0800
Subject: [PATCH] Tests for vpkd3d128 d3dcolor.

---
 .../frontend/ppc/test/bin/instr_vpkd3d128.bin | Bin 0 -> 112 bytes
 .../frontend/ppc/test/bin/instr_vpkd3d128.dis |  61 ++++++++
 .../frontend/ppc/test/bin/instr_vpkd3d128.map |  14 ++
 src/alloy/frontend/ppc/test/instr_vpkd3d128.s | 135 ++++++++++++++++++
 4 files changed, 210 insertions(+)
 create mode 100644 src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.bin
 create mode 100644 src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.dis
 create mode 100644 src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.map
 create mode 100644 src/alloy/frontend/ppc/test/instr_vpkd3d128.s

diff --git a/src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.bin b/src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.bin
new file mode 100644
index 0000000000000000000000000000000000000000..44bf995edb9139fd18748b3fb9599d1107ce2cd7
GIT binary patch
literal 112
zcmb1WloRl4U{H|2qywPh6QJ}3Fx>=I-y{c-Z<2$^H_1Wdo1yZ}Q2A!4d^1EI01Z$a
Aa{vGU

literal 0
HcmV?d00001

diff --git a/src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.dis b/src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.dis
new file mode 100644
index 000000000..82604fd17
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.dis
@@ -0,0 +1,61 @@
+
+/vagrant/src/alloy/frontend/ppc/test/bin//instr_vpkd3d128.o:     file format elf64-powerpc
+
+
+Disassembly of section .text:
+
+0000000000100000 <test_vpkd3d128_d3dcolor_invalid_0>:
+  100000:	18 81 1e 10 	vpkd3d128 v4,v3,0,0,0
+  100004:	4e 80 00 20 	blr
+
+0000000000100008 <test_vpkd3d128_d3dcolor_invalid_1>:
+  100008:	18 81 1e 10 	vpkd3d128 v4,v3,0,0,0
+  10000c:	4e 80 00 20 	blr
+
+0000000000100010 <test_vpkd3d128_d3dcolor_1_0>:
+  100010:	18 81 1e 10 	vpkd3d128 v4,v3,0,0,0
+  100014:	4e 80 00 20 	blr
+
+0000000000100018 <test_vpkd3d128_d3dcolor_1_1>:
+  100018:	18 81 1e 50 	vpkd3d128 v4,v3,0,0,0
+  10001c:	4e 80 00 20 	blr
+
+0000000000100020 <test_vpkd3d128_d3dcolor_1_2>:
+  100020:	18 81 1e 90 	vpkd3d128 v4,v3,0,0,2
+  100024:	4e 80 00 20 	blr
+
+0000000000100028 <test_vpkd3d128_d3dcolor_1_3>:
+  100028:	18 81 1e d0 	vpkd3d128 v4,v3,0,0,2
+  10002c:	4e 80 00 20 	blr
+
+0000000000100030 <test_vpkd3d128_d3dcolor_2_0>:
+  100030:	18 82 1e 10 	vpkd3d128 v4,v3,0,2,0
+  100034:	4e 80 00 20 	blr
+
+0000000000100038 <test_vpkd3d128_d3dcolor_2_1>:
+  100038:	18 82 1e 50 	vpkd3d128 v4,v3,0,2,0
+  10003c:	4e 80 00 20 	blr
+
+0000000000100040 <test_vpkd3d128_d3dcolor_2_2>:
+  100040:	18 82 1e 90 	vpkd3d128 v4,v3,0,2,2
+  100044:	4e 80 00 20 	blr
+
+0000000000100048 <test_vpkd3d128_d3dcolor_2_3>:
+  100048:	18 82 1e d0 	vpkd3d128 v4,v3,0,2,2
+  10004c:	4e 80 00 20 	blr
+
+0000000000100050 <test_vpkd3d128_d3dcolor_3_0>:
+  100050:	18 83 1e 10 	vpkd3d128 v4,v3,0,2,0
+  100054:	4e 80 00 20 	blr
+
+0000000000100058 <test_vpkd3d128_d3dcolor_3_1>:
+  100058:	18 83 1e 50 	vpkd3d128 v4,v3,0,2,0
+  10005c:	4e 80 00 20 	blr
+
+0000000000100060 <test_vpkd3d128_d3dcolor_3_2>:
+  100060:	18 83 1e 90 	vpkd3d128 v4,v3,0,2,2
+  100064:	4e 80 00 20 	blr
+
+0000000000100068 <test_vpkd3d128_d3dcolor_3_3>:
+  100068:	18 83 1e d0 	vpkd3d128 v4,v3,0,2,2
+  10006c:	4e 80 00 20 	blr
diff --git a/src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.map b/src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.map
new file mode 100644
index 000000000..f52351d9b
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/bin/instr_vpkd3d128.map
@@ -0,0 +1,14 @@
+0000000000000000 t test_vpkd3d128_d3dcolor_invalid_0
+0000000000000008 t test_vpkd3d128_d3dcolor_invalid_1
+0000000000000010 t test_vpkd3d128_d3dcolor_1_0
+0000000000000018 t test_vpkd3d128_d3dcolor_1_1
+0000000000000020 t test_vpkd3d128_d3dcolor_1_2
+0000000000000028 t test_vpkd3d128_d3dcolor_1_3
+0000000000000030 t test_vpkd3d128_d3dcolor_2_0
+0000000000000038 t test_vpkd3d128_d3dcolor_2_1
+0000000000000040 t test_vpkd3d128_d3dcolor_2_2
+0000000000000048 t test_vpkd3d128_d3dcolor_2_3
+0000000000000050 t test_vpkd3d128_d3dcolor_3_0
+0000000000000058 t test_vpkd3d128_d3dcolor_3_1
+0000000000000060 t test_vpkd3d128_d3dcolor_3_2
+0000000000000068 t test_vpkd3d128_d3dcolor_3_3
diff --git a/src/alloy/frontend/ppc/test/instr_vpkd3d128.s b/src/alloy/frontend/ppc/test/instr_vpkd3d128.s
new file mode 100644
index 000000000..ccb5d17d0
--- /dev/null
+++ b/src/alloy/frontend/ppc/test/instr_vpkd3d128.s
@@ -0,0 +1,135 @@
+# vpkd3d128 dest, src, type, mask, shift
+# type:
+#   0 = PACK_TYPE_D3DCOLOR
+#   1 = PACK_TYPE_SHORT_2
+#   3 = PACK_TYPE_FLOAT16_2
+#   5 = PACK_TYPE_FLOAT16_4
+# mask:
+#   must not be zero
+#   1 = 00000000 00000000 00000000 FFFFFFFF
+#   2 = 00000000 00000000 FFFFFFFF FFFFFFFF
+#   3 = same as 2? except mask3/shift3
+# shift:
+#   0 = no shift
+#   1 = shift left by one word
+#   2 ...
+#   3 ...
+# special case: mask3/shift3 = 00000000 00000000 00000000 FFFFFFFF
+
+# vpkd3d128 is broken in binutils, so these are hand coded
+
+test_vpkd3d128_d3dcolor_invalid_0:
+  #_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 1, 0
+  .long 0x18811E10
+  blr
+  #_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000]
+test_vpkd3d128_d3dcolor_invalid_1:
+  #_ REGISTER_IN v3 [40800000, 40000000, C2F60000, 4B3BDF83]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 1, 0
+  .long 0x18811E10
+  blr
+  #_ REGISTER_OUT v3 [40800000, 40000000, C2F60000, 4B3BDF83]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, FFFF0000]
+
+test_vpkd3d128_d3dcolor_1_0:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 1, 0
+  .long 0x18811E10
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
+test_vpkd3d128_d3dcolor_1_1:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 1, 1
+  .long 0x18811E50
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 04010203, CDCDCDCD]
+test_vpkd3d128_d3dcolor_1_2:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 1, 2
+  .long 0x18811E90
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, 04010203, CDCDCDCD, CDCDCDCD]
+test_vpkd3d128_d3dcolor_1_3:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 1, 3
+  .long 0x18811ED0
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [04010203, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+
+test_vpkd3d128_d3dcolor_2_0:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 2, 0
+  .long 0x18821E10
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 00000000, 04010203]
+test_vpkd3d128_d3dcolor_2_1:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 2, 1
+  .long 0x18821E50
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, 00000000, 04010203, CDCDCDCD]
+test_vpkd3d128_d3dcolor_2_2:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 2, 2
+  .long 0x18821E90
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [00000000, 04010203, CDCDCDCD, CDCDCDCD]
+test_vpkd3d128_d3dcolor_2_3:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 2, 3
+  .long 0x18821ED0
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [04010203, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+
+test_vpkd3d128_d3dcolor_3_0:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 3, 0
+  .long 0x18831E10
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 00000000, 04010203]
+test_vpkd3d128_d3dcolor_3_1:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 3, 1
+  .long 0x18831E50
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, 00000000, 04010203, CDCDCDCD]
+test_vpkd3d128_d3dcolor_3_2:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 3, 2
+  .long 0x18831E90
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [00000000, 04010203, CDCDCDCD, CDCDCDCD]
+test_vpkd3d128_d3dcolor_3_3:
+  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
+  # vpkd3d128 v4, v3, 0, 3, 3
+  .long 0x18831ED0
+  blr
+  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
+  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000]