ShuriZma
/
xenia-canary
mirror of https://github.com/xenia-canary/xenia-canary.git
1
0
Fork 0
Code Issues Packages Projects Releases Wiki Activity

CR0 tests for addze.

This commit is contained in:
gibbed 2015-05-14 01:43:18 -05:00
parent e4f8818d07
commit 30f4556baf
1 changed files with 200 additions and 0 deletions
Show Stats Download Patch File Download Diff File Expand all files Collapse all files

200
src/xenia/cpu/frontend/test/instr_addze.s
View File

@ -165,3 +165,203 @@ test_addze_8_constant:
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
test_addze_cr_1:
#_ REGISTER_IN r4 1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_1_constant:
li r4, 1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_2:
#_ REGISTER_IN r4 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_2_constant:
li r4, 1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 2
#_ REGISTER_OUT r4 1
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_3:
#_ REGISTER_IN r4 12
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 12
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_3_constant:
li r4, 12
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 12
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_4:
#_ REGISTER_IN r4 12
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 13
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_4_constant:
li r4, 12
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 13
#_ REGISTER_OUT r4 12
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_5:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x80000000
test_addze_cr_5_constant:
li r4, -1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x80000000
test_addze_cr_6:
#_ REGISTER_IN r4 0xFFFFFFFFFFFFFFFF
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x20000000
test_addze_cr_6_constant:
li r4, -1
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0xFFFFFFFFFFFFFFFF
#_ REGISTER_OUT r6 1
#_ REGISTER_OUT r12 0x20000000
test_addze_cr_7:
#_ REGISTER_IN r4 0
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x20000000
test_addze_cr_7_constant:
li r4, 0
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 0
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x20000000
test_addze_cr_8:
#_ REGISTER_IN r4 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000
test_addze_cr_8_constant:
li r4, 0
xor r3, r3, r3
not r3, r3
addic r3, r3, 1 # CA=1
addze. r3, r4
adde r6, r0, r0
mfcr r12
blr
#_ REGISTER_OUT r3 1
#_ REGISTER_OUT r4 0
#_ REGISTER_OUT r6 0
#_ REGISTER_OUT r12 0x40000000