[GPU] Document memexport/resolve formats with more details
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Triang3l
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d6660ac391
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28fec845d5
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@ -876,8 +876,9 @@ bool GetResolveInfo(const RegisterFile& regs, const Memory& memory,
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}
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info_out.address.copy_sample_select = sample_select;
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// Get the format to pass to the shader in a unified way - for depth (for
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// which Direct3D 9 specifies the k_8_8_8_8 destination format), make sure the
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// shader won't try to do conversion - pass proper k_24_8 or k_24_8_FLOAT.
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// which Direct3D 9 specifies the k_8_8_8_8 uint destination format), make
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// sure the shader won't try to do conversion - pass proper k_24_8 or
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// k_24_8_FLOAT.
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auto rb_copy_dest_info = regs.Get<reg::RB_COPY_DEST_INFO>();
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xenos::TextureFormat dest_format;
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auto rb_depth_info = regs.Get<reg::RB_DEPTH_INFO>();
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@ -15,6 +15,14 @@ namespace xe {
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namespace gpu {
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using namespace ucode;
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// TODO(Triang3l): Support sub-dword memexports (like k_8 in 58410B86). This
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// would require four 128 MB R8_UINT UAVs due to the Nvidia addressing limit.
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// Need to be careful with resource binding tiers, however. Resource binding
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// tier 1 on feature level 11_0 allows only 8 UAVs _across all stages_.
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// RWByteAddressBuffer + 4 typed buffers is 5 per stage already, would need 10
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// for both VS and PS, or even 11 with the eDRAM ROV. Need to drop draw commands
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// doing memexport in both VS and PS on FL 11_0 resource binding tier 1.
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void DxbcShaderTranslator::ExportToMemory_PackFixed32(
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const uint32_t* eM_temps, uint32_t eM_count, const uint32_t bits[4],
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const dxbc::Src& is_integer, const dxbc::Src& is_signed) {
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@ -712,14 +712,14 @@ static_assert_size(RB_COPY_CONTROL, sizeof(uint32_t));
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union alignas(uint32_t) RB_COPY_DEST_INFO {
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struct {
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xenos::Endian128 copy_dest_endian : 3; // +0
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uint32_t copy_dest_array : 1; // +3
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uint32_t copy_dest_slice : 3; // +4
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xenos::ColorFormat copy_dest_format : 6; // +7
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uint32_t copy_dest_number : 3; // +13
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int32_t copy_dest_exp_bias : 6; // +16
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uint32_t : 2; // +22
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uint32_t copy_dest_swap : 1; // +24
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xenos::Endian128 copy_dest_endian : 3; // +0
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uint32_t copy_dest_array : 1; // +3
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uint32_t copy_dest_slice : 3; // +4
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xenos::ColorFormat copy_dest_format : 6; // +7
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xenos::SurfaceNumberFormat copy_dest_number : 3; // +13
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int32_t copy_dest_exp_bias : 6; // +16
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uint32_t : 2; // +22
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uint32_t copy_dest_swap : 1; // +24
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};
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uint32_t value;
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static constexpr Register register_index = XE_GPU_REG_RB_COPY_DEST_INFO;
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@ -185,7 +185,7 @@ enum class IndexFormat : uint32_t {
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};
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// SurfaceNumberX from yamato_enum.h.
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enum class SurfaceNumFormat : uint32_t {
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enum class SurfaceNumberFormat : uint32_t {
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kUnsignedRepeatingFraction = 0,
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// Microsoft-style, scale factor (2^(n-1))-1.
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kSignedRepeatingFraction = 1,
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@ -1176,14 +1176,120 @@ union alignas(uint32_t) xe_gpu_fetch_group_t {
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};
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static_assert_size(xe_gpu_fetch_group_t, sizeof(uint32_t) * 6);
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// GPU_MEMEXPORT_STREAM_CONSTANT from a game .pdb - float constant for memexport
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// stream configuration.
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// This is used with the floating-point ALU in shaders (written to eA using
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// mad), so the dwords have a normalized exponent when reinterpreted as floats
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// (otherwise they would be flushed to zero), but actually these are packed
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// integers. dword_1 specifically is 2^23 because
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// powf(2.0f, 23.0f) + float(i) == 0x4B000000 | i
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// so mad can pack indices as integers in the lower bits.
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// Shader memory export (memexport) allows for writing of arbitrary formatted
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// data with random access / scatter capabilities. It provides functionality
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// largely similar to resolving - format packing, supporting arbitrary color
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// formats, from sub-dword ones such as k_8 in 58410B86, to 128-bit ones, with
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// endian swap similar to how it's performed in resolves (up to 128-bit);
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// specifying the number format, swapping red and blue channels - though with no
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// exponent biasing. Unlike resolving, however, instead of writing to tiled
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// textures, it exports the data to up to 5 elements (the eM# shader registers,
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// each corresponding to `base address + element size * (offset + 0...4)`) in a
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// stream defined by a stream constant and an offset in elements written to eA -
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// a shader, however, can write to multiple streams with different or the same
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// stream constants, by performing `alloc export` multiple times. It's used
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// mostly in vertex shaders (most commonly in improvised "compute shaders" done
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// by executing a vertex shader for a number of point-type primitives covering
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// nothing), though usage in pixel shaders is also possible - an example is
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// provided in the "Advanced Screenspace Antialiasing" presentation by Arne
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// Schober.
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// https://ubm-twvideo01.s3.amazonaws.com/o1/vault/gdceurope2010/slides/A_Schober_Advanced_Screenspace_Antialiasing.pdf
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//
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// Unlike fetch constants, which are passed via special registers, a memory
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// export stream is configured by writing the stream constant and the offset to
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// a shader export register (eA) allocated by the shader - similar to more
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// conventional exports like oPos, o#, oC#. Therefore, in general, it's not
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// possible to know what its value will be without running the shader. For
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// emulation, this means that the memory range referenced by an export - that
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// needs to be validated - requires running the shader on the CPU in general.
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// Thankfully, however, the usual way of setting up eA is by executing:
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// `mad eA, r#, const0100, c#`
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// where c# is the stream float4 constant from the float constant registers, and
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// const0100 is a literal (0.0f, 1.0f, 0.0f, 0.0f) constant, also from the float
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// constant registers, used for placing the element index (r#) in the correct
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// component of eA. This allows for easy gathering of memexport stream
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// constants, which contain both the base address and the size of the
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// destination buffer for bounds checking, from the shader code and the float
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// constant registers, as long as the guest uses this instruction pattern to
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// write to eA.
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//
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// The Xenos doesn't have an integer ALU, and denormals are treated as zero and
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// are flushed. However, eA contains integers and bit fields. A stream constant
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// is thus structured in a way that allows for packing integers in normalized
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// floating-point numbers.
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//
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// X contains the base address of the stream in dwords as integer bits in the
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// lower 30 bits, and bits 0b01 in the top. The 0b01 bits make the exponent
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// nonzero, so the number is considered normalized, and therefore isn't flushed
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// to zero. With only 512 MB of the physical memory on the Xbox 360, the
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// exponent can't become 0b11111111, so X also won't be NaN for any valid Xbox
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// 360 physical address (though in general the GPU supports 32-bit addresses,
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// but this is originally an Xbox 360-specific feature, that was later, however,
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// likely reused for GL_QCOM_writeonly_rendering).
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//
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// TODO(Triang3l): Verify whether GL_QCOM_writeonly_rendering is actually
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// memexport on the Adreno 2xx using GL_OES_get_program_binary - it's also
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// interesting to see how alphatest interacts with it, whether it's still true
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// fixed-function alphatest, as it's claimed to be supported as usual by the
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// extension specification - it's likely, however, that memory exports are
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// discarded alongside other exports such as oC# and oDepth this way.
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//
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// Y of eA contains the offset in elements - this is what shaders are supposed
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// to calculate from something like the vertex index. Again, it's specified as
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// an integer in the low bits, not as a truly floating-point number. For this
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// purpose, stream constants contain the value 2^23 - when a whole
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// floating-point number smaller than 2^23 is added as floating-point to 2^23,
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// its integer representation becomes the mantissa bits of a number with an
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// exponent of 23. Via multiply-add, `offset * 1.0f + exp2f(23)` is written here
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// by the shader, allowing for element offsets of up to 2^23 - 1.
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//
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// Z is a bit field with the information about the formatting of the data. It's
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// also packed as a normalized floating-point number, but in a cleaner way than
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// X because not as many bits are required - just like Y, it has an exponent of
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// 23 (possibly to let shaders build these values manually using floating-point
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// multiply-add like integer shift-or, and finally to add 2^23, though that's
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// not a case easy to handle in emulation, unlike prebuilt stream constants).
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//
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// W contains the number of elements in the stream. It's also packed with the
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// full 23 exponent just like Y and Z, there's no way to index more than 2^23
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// elements using packing via addition to 2^23, so this field also doesn't need
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// more bits than that.
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//
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// Examples of setup in titles (Z from MSB to LSB):
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//
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// 4D5307E6 particles (different VS invocation counts, like 1, 2, 4):
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// There is a passthrough shader - useful for verification as it simply writes
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// directly what it reads via vfetch of various formats. Another shader (with
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// different c# numbers, but same formats) does complicated math to process the
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// particles.
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// c152: Z = 010010110000|0|111|00|100110|00000|010, count = 35840
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// 8in32, 32_32_32_32_FLOAT, float, RGBA - from 32_32_32_32_FLOAT vfetch
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// c154, 162: Z = 010010110000|0|111|00|100000|00000|001, count = 71680
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// 8in16, 16_16_16_16_FLOAT, float, RGBA - from 16_16_16_16_FLOAT vfetch
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// c156, 158, 160: Z = 010010110000|0|000|00|011010|00000|001, count = 71680
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// 8in16, 16_16_16_16, unorm, RGBA - from 16_16_16_16 unorm vfetch
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// c164: Z = 010010110000|0|111|00|011111|00000|001, count = 143360
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// 8in16, 16_16_FLOAT, float, RGBA - from 16_16_FLOAT vfetch
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// c166: Z = 010010110000|0|000|00|011001|00000|001, count = 143360
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// 8in16, 16_16, unorm, RGBA - from 16_16 unorm vfetch
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// c168: Z = 010010110000|0|001|00|000111|00000|010, count = 143360
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// 8in32, 2_10_10_10, snorm, RGBA - from 2_10_10_10 snorm vfetch
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// c170, c172: Z = 010010110000|1|000|00|000110|00000|010, count = 143360
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// 8in32, 8_8_8_8, unorm, BGRA - from 8_8_8_8 unorm vfetch with .zyxw swizzle
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//
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// 4D5307E6 water simulation (2048 VS invocations):
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// c130: Z = 010010110000|0|111|00|100110|00000|010, count = 16384
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// 8in32, 32_32_32_32_FLOAT, float, RGBA
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// The shader has 5 memexports of this kind and 6 32_32_32_32_FLOAT vfetches.
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//
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// 4D5307E6 water tessellation factors (1 VS invocation per triangle patch):
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// c130: Z = 010010110000|0|111|11|100100|11111|010, count = patch count * 3
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// 8in32, 32_FLOAT, float, RGBA
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//
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// 41560817 texture memory copying (64 bytes per invocation, two eA, eight eM#):
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// c0: Z = 010010110000|0|010|11|011010|00011|001
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// 8in16, 16_16_16_16, uint, RGBA - from 16_16_16_16 uint vfetch
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// (16_16_16_16 is the largest color format without special values)
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union alignas(uint32_t) xe_gpu_memexport_stream_t {
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struct {
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uint32_t base_address : 30; // +0 dword_0 physical address >> 2
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@ -1191,13 +1297,13 @@ union alignas(uint32_t) xe_gpu_memexport_stream_t {
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uint32_t const_0x4b000000; // +0 dword_1
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Endian128 endianness : 3; // +0 dword_2
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uint32_t unused_0 : 5; // +3
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ColorFormat format : 6; // +8
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uint32_t unused_1 : 2; // +14
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SurfaceNumFormat num_format : 3; // +16
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uint32_t red_blue_swap : 1; // +19
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uint32_t const_0x4b0 : 12; // +20
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Endian128 endianness : 3; // +0 dword_2
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uint32_t unused_0 : 5; // +3
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ColorFormat format : 6; // +8
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uint32_t unused_1 : 2; // +14
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SurfaceNumberFormat num_format : 3; // +16
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uint32_t red_blue_swap : 1; // +19
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uint32_t const_0x4b0 : 12; // +20
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uint32_t index_count : 23; // +0 dword_3
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uint32_t const_0x96 : 9; // +23
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