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Moving test memory to a more reasonable place.

This commit is contained in:
Ben Vanik 2015-08-18 09:01:22 -07:00
parent c6b941a709
commit 2820ff85e5
8 changed files with 138 additions and 121 deletions
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78
src/xenia/cpu/frontend/testing/instr_lvexx.s
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@ -1,95 +1,101 @@
test_lvebx_1: test_lvebx_1:
#_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f #_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0x00001000 #_ REGISTER_IN r4 0x10001000
lvebx v3, r0, r4 lvebx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x00001000 #_ REGISTER_OUT r4 0x10001000
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvebx_1_constant: test_lvebx_1_constant:
#_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f #_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
li r4, 0x00001000 lis r4, 0x1000
ori r4, r4, 0x1000
lvebx v3, r0, r4 lvebx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x00001000 #_ REGISTER_OUT r4 0x10001000
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvebx_2: test_lvebx_2:
#_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f #_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0x00001004 #_ REGISTER_IN r4 0x10001004
lvebx v3, r0, r4 lvebx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x00001004 #_ REGISTER_OUT r4 0x10001004
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvebx_2_constant: test_lvebx_2_constant:
#_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f #_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
li r4, 0x00001004 lis r4, 0x1000
ori r4, r4, 0x1004
lvebx v3, r0, r4 lvebx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x00001004 #_ REGISTER_OUT r4 0x10001004
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvehx_1: test_lvehx_1:
#_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f #_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0x00001000 #_ REGISTER_IN r4 0x10001000
lvehx v3, r0, r4 lvehx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x00001000 #_ REGISTER_OUT r4 0x10001000
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvehx_1_constant: test_lvehx_1_constant:
#_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f #_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
li r4, 0x00001000 lis r4, 0x1000
ori r4, r4, 0x1000
lvehx v3, r0, r4 lvehx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x00001000 #_ REGISTER_OUT r4 0x10001000
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvehx_2: test_lvehx_2:
#_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f #_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0x00001004 #_ REGISTER_IN r4 0x10001004
lvehx v3, r0, r4 lvehx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x00001004 #_ REGISTER_OUT r4 0x10001004
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvehx_2_constant: test_lvehx_2_constant:
#_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f #_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
li r4, 0x00001004 lis r4, 0x1000
ori r4, r4, 0x1004
lvehx v3, r0, r4 lvehx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x00001004 #_ REGISTER_OUT r4 0x10001004
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx_1: test_lvewx_1:
#_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f #_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0x00001000 #_ REGISTER_IN r4 0x10001000
lvewx v3, r0, r4 lvewx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x00001000 #_ REGISTER_OUT r4 0x10001000
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx_1_constant: test_lvewx_1_constant:
#_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f #_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
li r4, 0x00001000 lis r4, 0x1000
ori r4, r4, 0x1000
lvewx v3, r0, r4 lvewx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x00001000 #_ REGISTER_OUT r4 0x10001000
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx_2: test_lvewx_2:
#_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f #_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
#_ REGISTER_IN r4 0x00001004 #_ REGISTER_IN r4 0x10001004
lvewx v3, r0, r4 lvewx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x00001004 #_ REGISTER_OUT r4 0x10001004
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
test_lvewx_2_constant: test_lvewx_2_constant:
#_ MEMORY_IN 00001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f #_ MEMORY_IN 10001000 00 01 02 03 04 05 06 07 08 09 0a 0b 0c 0d 0e 0f
li r4, 0x00001004 lis r4, 0x1000
ori r4, r4, 0x1004
lvewx v3, r0, r4 lvewx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x00001004 #_ REGISTER_OUT r4 0x10001004
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]

13
src/xenia/cpu/frontend/testing/instr_lvl.s
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@ -1,15 +1,16 @@
test_lvl_1: test_lvl_1:
#_ MEMORY_IN 00001077 0a 0b 0c 0d 0e 0f 10 13 0c 0d 0e 10 11 12 13 14 ff ff ff ff ff ff #_ MEMORY_IN 10001077 0a 0b 0c 0d 0e 0f 10 13 0c 0d 0e 10 11 12 13 14 ff ff ff ff ff ff
#_ REGISTER_IN r4 0x1077 #_ REGISTER_IN r4 0x10001077
lvlx v3, r4, r0 lvlx v3, r4, r0
blr blr
#_ REGISTER_OUT r4 0x1077 #_ REGISTER_OUT r4 0x10001077
#_ REGISTER_OUT v3 [0A0B0C0D, 0E0F1013, 0C000000, 00000000] #_ REGISTER_OUT v3 [0A0B0C0D, 0E0F1013, 0C000000, 00000000]
test_lvl_1_constant: test_lvl_1_constant:
#_ MEMORY_IN 00001077 0a 0b 0c 0d 0e 0f 10 13 0c 0d 0e 10 11 12 13 14 ff ff ff ff ff ff #_ MEMORY_IN 10001077 0a 0b 0c 0d 0e 0f 10 13 0c 0d 0e 10 11 12 13 14 ff ff ff ff ff ff
li r4, 0x1077 lis r4, 0x1000
ori r4, r4, 0x1077
lvlx v3, r4, r0 lvlx v3, r4, r0
blr blr
#_ REGISTER_OUT r4 0x1077 #_ REGISTER_OUT r4 0x10001077
#_ REGISTER_OUT v3 [0A0B0C0D, 0E0F1013, 0C000000, 00000000] #_ REGISTER_OUT v3 [0A0B0C0D, 0E0F1013, 0C000000, 00000000]

13
src/xenia/cpu/frontend/testing/instr_lvr.s
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@ -1,19 +1,20 @@
test_lvr_1: test_lvr_1:
#_ MEMORY_IN 000010B0 090A0A0B 0C0F120A 0B0C0D0E 0F10130C 0D0E1011 121314FF FFFFFFFF #_ MEMORY_IN 100010B0 090A0A0B 0C0F120A 0B0C0D0E 0F10130C 0D0E1011 121314FF FFFFFFFF
#_ REGISTER_IN r4 0x10B7 #_ REGISTER_IN r4 0x100010B7
#_ REGISTER_IN r5 0x10 #_ REGISTER_IN r5 0x10
lvrx v3, r4, r5 lvrx v3, r4, r5
blr blr
#_ REGISTER_OUT r4 0x10B7 #_ REGISTER_OUT r4 0x100010B7
#_ REGISTER_OUT r5 0x10 #_ REGISTER_OUT r5 0x10
#_ REGISTER_OUT v3 [00000000, 00000000, 000D0E10, 11121314] #_ REGISTER_OUT v3 [00000000, 00000000, 000D0E10, 11121314]
test_lvr_1_constant: test_lvr_1_constant:
#_ MEMORY_IN 000010B0 090A0A0B 0C0F120A 0B0C0D0E 0F10130C 0D0E1011 121314FF FFFFFFFF #_ MEMORY_IN 100010B0 090A0A0B 0C0F120A 0B0C0D0E 0F10130C 0D0E1011 121314FF FFFFFFFF
li r4, 0x10B7 lis r4, 0x1000
ori r4, r4, 0x10B7
li r5, 0x10 li r5, 0x10
lvrx v3, r4, r5 lvrx v3, r4, r5
blr blr
#_ REGISTER_OUT r4 0x10B7 #_ REGISTER_OUT r4 0x100010B7
#_ REGISTER_OUT r5 0x10 #_ REGISTER_OUT r5 0x10
#_ REGISTER_OUT v3 [00000000, 00000000, 000D0E10, 11121314] #_ REGISTER_OUT v3 [00000000, 00000000, 000D0E10, 11121314]

68
src/xenia/cpu/frontend/testing/instr_stvew.s
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@ -1,79 +1,83 @@
test_stvew_1: test_stvew_1:
#_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC #_ MEMORY_IN 10001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
#_ REGISTER_IN r4 0x1050 #_ REGISTER_IN r4 0x10001050
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
stvewx v3, r0, r4 stvewx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x1050 #_ REGISTER_OUT r4 0x10001050
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ MEMORY_OUT 00001050 00010203 CCCCCCCC CCCCCCCC CCCCCCCC #_ MEMORY_OUT 10001050 00010203 CCCCCCCC CCCCCCCC CCCCCCCC
test_stvew_1_constant: test_stvew_1_constant:
#_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC #_ MEMORY_IN 10001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
li r4, 0x1050 lis r4, 0x1000
ori r4, r4, 0x1050
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
stvewx v3, r0, r4 stvewx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x1050 #_ REGISTER_OUT r4 0x10001050
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ MEMORY_OUT 00001050 00010203 CCCCCCCC CCCCCCCC CCCCCCCC #_ MEMORY_OUT 10001050 00010203 CCCCCCCC CCCCCCCC CCCCCCCC
test_stvew_2: test_stvew_2:
#_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC #_ MEMORY_IN 10001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
#_ REGISTER_IN r4 0x1054 #_ REGISTER_IN r4 0x10001054
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
stvewx v3, r0, r4 stvewx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x1054 #_ REGISTER_OUT r4 0x10001054
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ MEMORY_OUT 00001050 CCCCCCCC 04050607 CCCCCCCC CCCCCCCC #_ MEMORY_OUT 10001050 CCCCCCCC 04050607 CCCCCCCC CCCCCCCC
test_stvew_2_constant: test_stvew_2_constant:
#_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC #_ MEMORY_IN 10001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
li r4, 0x1054 lis r4, 0x1000
ori r4, r4, 0x1054
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
stvewx v3, r0, r4 stvewx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x1054 #_ REGISTER_OUT r4 0x10001054
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ MEMORY_OUT 00001050 CCCCCCCC 04050607 CCCCCCCC CCCCCCCC #_ MEMORY_OUT 10001050 CCCCCCCC 04050607 CCCCCCCC CCCCCCCC
test_stvew_3: test_stvew_3:
#_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC #_ MEMORY_IN 10001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
#_ REGISTER_IN r4 0x1058 #_ REGISTER_IN r4 0x10001058
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
stvewx v3, r0, r4 stvewx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x1058 #_ REGISTER_OUT r4 0x10001058
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ MEMORY_OUT 00001050 CCCCCCCC CCCCCCCC 08090A0B CCCCCCCC #_ MEMORY_OUT 10001050 CCCCCCCC CCCCCCCC 08090A0B CCCCCCCC
test_stvew_3_constant: test_stvew_3_constant:
#_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC #_ MEMORY_IN 10001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
li r4, 0x1058 lis r4, 0x1000
ori r4, r4, 0x1058
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
stvewx v3, r0, r4 stvewx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x1058 #_ REGISTER_OUT r4 0x10001058
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ MEMORY_OUT 00001050 CCCCCCCC CCCCCCCC 08090A0B CCCCCCCC #_ MEMORY_OUT 10001050 CCCCCCCC CCCCCCCC 08090A0B CCCCCCCC
test_stvew_4: test_stvew_4:
#_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC #_ MEMORY_IN 10001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
#_ REGISTER_IN r4 0x105C #_ REGISTER_IN r4 0x1000105C
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
stvewx v3, r0, r4 stvewx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x105C #_ REGISTER_OUT r4 0x1000105C
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ MEMORY_OUT 00001050 CCCCCCCC CCCCCCCC CCCCCCCC 0C0D0E0F #_ MEMORY_OUT 10001050 CCCCCCCC CCCCCCCC CCCCCCCC 0C0D0E0F
test_stvew_4_constant: test_stvew_4_constant:
#_ MEMORY_IN 00001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC #_ MEMORY_IN 10001050 CCCCCCCC CCCCCCCC CCCCCCCC CCCCCCCC
li r4, 0x105C lis r4, 0x1000
ori r4, r4, 0x105C
#_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_IN v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
stvewx v3, r0, r4 stvewx v3, r0, r4
blr blr
#_ REGISTER_OUT r4 0x105C #_ REGISTER_OUT r4 0x1000105C
#_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F] #_ REGISTER_OUT v3 [00010203, 04050607, 08090A0B, 0C0D0E0F]
#_ MEMORY_OUT 00001050 CCCCCCCC CCCCCCCC CCCCCCCC 0C0D0E0F #_ MEMORY_OUT 10001050 CCCCCCCC CCCCCCCC CCCCCCCC 0C0D0E0F

34
src/xenia/cpu/frontend/testing/instr_stvl.s
View File

@ -1,39 +1,41 @@
test_stvl_1: test_stvl_1:
#_ MEMORY_IN 00001040 00000000 00000000 00000000 3F800000 #_ MEMORY_IN 10001040 00000000 00000000 00000000 3F800000
#_ REGISTER_IN r4 0x1040 #_ REGISTER_IN r4 0x10001040
#_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F] #_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
stvlx v3, r4, r0 stvlx v3, r4, r0
blr blr
#_ REGISTER_OUT r4 0x1040 #_ REGISTER_OUT r4 0x10001040
#_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F] #_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
#_ MEMORY_OUT 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F #_ MEMORY_OUT 10001040 BE74FCBD BD912ABA BF317BBB BF2D135F
test_stvl_1_constant: test_stvl_1_constant:
#_ MEMORY_IN 00001040 00000000 00000000 00000000 3F800000 #_ MEMORY_IN 10001040 00000000 00000000 00000000 3F800000
li r4, 0x1040 lis r4, 0x1000
ori r4, r4, 0x1040
#_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F] #_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
stvlx v3, r4, r0 stvlx v3, r4, r0
blr blr
#_ REGISTER_OUT r4 0x1040 #_ REGISTER_OUT r4 0x10001040
#_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F] #_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
#_ MEMORY_OUT 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F #_ MEMORY_OUT 10001040 BE74FCBD BD912ABA BF317BBB BF2D135F
test_stvl_2: test_stvl_2:
#_ MEMORY_IN 00001040 00010203 04050607 08090A0B 0C0D0E0F #_ MEMORY_IN 10001040 00010203 04050607 08090A0B 0C0D0E0F
#_ REGISTER_IN r4 0x1044 #_ REGISTER_IN r4 0x10001044
#_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF] #_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
stvlx v3, r4, r0 stvlx v3, r4, r0
blr blr
#_ REGISTER_OUT r4 0x1044 #_ REGISTER_OUT r4 0x10001044
#_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF] #_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
#_ MEMORY_OUT 00001040 00010203 F0F1F2F3 F4F5F6F7 F8F9FAFB #_ MEMORY_OUT 10001040 00010203 F0F1F2F3 F4F5F6F7 F8F9FAFB
test_stvl_2_constant: test_stvl_2_constant:
#_ MEMORY_IN 00001040 00010203 04050607 08090A0B 0C0D0E0F #_ MEMORY_IN 10001040 00010203 04050607 08090A0B 0C0D0E0F
li r4, 0x1044 lis r4, 0x1000
ori r4, r4, 0x1044
#_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF] #_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
stvlx v3, r4, r0 stvlx v3, r4, r0
blr blr
#_ REGISTER_OUT r4 0x1044 #_ REGISTER_OUT r4 0x10001044
#_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF] #_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
#_ MEMORY_OUT 00001040 00010203 F0F1F2F3 F4F5F6F7 F8F9FAFB #_ MEMORY_OUT 10001040 00010203 F0F1F2F3 F4F5F6F7 F8F9FAFB

42
src/xenia/cpu/frontend/testing/instr_stvr.s
View File

@ -1,47 +1,49 @@
test_stvr_1: test_stvr_1:
#_ MEMORY_IN 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F #_ MEMORY_IN 10001040 BE74FCBD BD912ABA BF317BBB BF2D135F
#_ MEMORY_IN 00001050 00000000 00000000 00000000 00000000 #_ MEMORY_IN 10001050 00000000 00000000 00000000 00000000
#_ REGISTER_IN r4 0x1040 #_ REGISTER_IN r4 0x10001040
#_ REGISTER_IN r5 0x10 #_ REGISTER_IN r5 0x10
#_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F] #_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
stvrx v3, r4, r5 stvrx v3, r4, r5
blr blr
#_ REGISTER_OUT r4 0x1040 #_ REGISTER_OUT r4 0x10001040
#_ REGISTER_OUT r5 0x10 #_ REGISTER_OUT r5 0x10
#_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F] #_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
#_ MEMORY_OUT 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F #_ MEMORY_OUT 10001040 BE74FCBD BD912ABA BF317BBB BF2D135F
#_ MEMORY_OUT 00001050 00000000 00000000 00000000 00000000 #_ MEMORY_OUT 10001050 00000000 00000000 00000000 00000000
test_stvr_1_constant: test_stvr_1_constant:
#_ MEMORY_IN 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F #_ MEMORY_IN 10001040 BE74FCBD BD912ABA BF317BBB BF2D135F
#_ MEMORY_IN 00001050 00000000 00000000 00000000 00000000 #_ MEMORY_IN 10001050 00000000 00000000 00000000 00000000
li r4, 0x1040 lis r4, 0x1000
ori r4, r4, 0x1040
li r5, 0x10 li r5, 0x10
#_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F] #_ REGISTER_IN v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
stvrx v3, r4, r5 stvrx v3, r4, r5
blr blr
#_ REGISTER_OUT r4 0x1040 #_ REGISTER_OUT r4 0x10001040
#_ REGISTER_OUT r5 0x10 #_ REGISTER_OUT r5 0x10
#_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F] #_ REGISTER_OUT v3 [BE74FCBD, BD912ABA, BF317BBB, BF2D135F]
#_ MEMORY_OUT 00001040 BE74FCBD BD912ABA BF317BBB BF2D135F #_ MEMORY_OUT 10001040 BE74FCBD BD912ABA BF317BBB BF2D135F
#_ MEMORY_OUT 00001050 00000000 00000000 00000000 00000000 #_ MEMORY_OUT 10001050 00000000 00000000 00000000 00000000
test_stvr_2: test_stvr_2:
#_ MEMORY_IN 00001040 00010203 04050607 08090A0B 0C0D0E0F #_ MEMORY_IN 10001040 00010203 04050607 08090A0B 0C0D0E0F
#_ REGISTER_IN r4 0x1044 #_ REGISTER_IN r4 0x10001044
#_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF] #_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
stvrx v3, r4, r0 stvrx v3, r4, r0
blr blr
#_ REGISTER_OUT r4 0x1044 #_ REGISTER_OUT r4 0x10001044
#_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF] #_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
#_ MEMORY_OUT 00001040 FCFDFEFF 04050607 08090A0B 0C0D0E0F #_ MEMORY_OUT 10001040 FCFDFEFF 04050607 08090A0B 0C0D0E0F
test_stvr_2_constant: test_stvr_2_constant:
#_ MEMORY_IN 00001040 00010203 04050607 08090A0B 0C0D0E0F #_ MEMORY_IN 10001040 00010203 04050607 08090A0B 0C0D0E0F
li r4, 0x1044 lis r4, 0x1000
ori r4, r4, 0x1044
#_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF] #_ REGISTER_IN v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
stvrx v3, r4, r0 stvrx v3, r4, r0
blr blr
#_ REGISTER_OUT r4 0x1044 #_ REGISTER_OUT r4 0x10001044
#_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF] #_ REGISTER_OUT v3 [F0F1F2F3, F4F5F6F7, F8F9FAFB, FCFDFEFF]
#_ MEMORY_OUT 00001040 FCFDFEFF 04050607 08090A0B 0C0D0E0F #_ MEMORY_OUT 10001040 FCFDFEFF 04050607 08090A0B 0C0D0E0F

3
src/xenia/cpu/frontend/testing/ppc_testing_main.cc
View File

@ -202,7 +202,8 @@ class TestRunner {
// Add dummy space for memory. // Add dummy space for memory.
processor->memory()->LookupHeap(0)->AllocFixed( processor->memory()->LookupHeap(0)->AllocFixed(
0x1000, 0xEFFF, 0, kMemoryAllocationReserve | kMemoryAllocationCommit, 0x10001000, 0xEFFF, 0,
kMemoryAllocationReserve | kMemoryAllocationCommit,
kMemoryProtectRead | kMemoryProtectWrite); kMemoryProtectRead | kMemoryProtectWrite);
// Simulate a thread. // Simulate a thread.

8
src/xenia/cpu/frontend/testing/sequence_branch_carry.s
View File

@ -4,7 +4,7 @@ test_equiv_1:
ori r30, r9, 0x83C1 # 0x9E2A83C1 ori r30, r9, 0x83C1 # 0x9E2A83C1
subf r8, r11, r30 subf r8, r11, r30
addic r7, r8, -1 addic r7, r8, -1
subfe. r31, r7, r8 subfe. r29, r7, r8
beq equiv_1_good beq equiv_1_good
li r12, 0 li r12, 0
blr blr
@ -15,7 +15,7 @@ equiv_1_good:
#_ REGISTER_OUT r8 0xffffffff00000000 #_ REGISTER_OUT r8 0xffffffff00000000
#_ REGISTER_OUT r9 0xffffffff9e2a0000 #_ REGISTER_OUT r9 0xffffffff9e2a0000
#_ REGISTER_OUT r30 0xffffffff9e2a83c1 #_ REGISTER_OUT r30 0xffffffff9e2a83c1
#_ REGISTER_OUT r31 0 #_ REGISTER_OUT r29 0
#_ REGISTER_OUT r11 0x000000009e2a83c1 #_ REGISTER_OUT r11 0x000000009e2a83c1
#_ REGISTER_OUT r12 1 #_ REGISTER_OUT r12 1
@ -25,7 +25,7 @@ test_equiv_2:
ori r30, r9, 0x83C1 # 0x9E2A83C1 ori r30, r9, 0x83C1 # 0x9E2A83C1
subf r8, r11, r30 subf r8, r11, r30
addic r7, r8, -1 addic r7, r8, -1
subfe. r31, r7, r8 subfe. r29, r7, r8
beq equiv_2_good beq equiv_2_good
li r12, 0 li r12, 0
blr blr
@ -36,6 +36,6 @@ equiv_2_good:
#_ REGISTER_OUT r8 0 #_ REGISTER_OUT r8 0
#_ REGISTER_OUT r9 0xffffffff9e2a0000 #_ REGISTER_OUT r9 0xffffffff9e2a0000
#_ REGISTER_OUT r30 0xffffffff9e2a83c1 #_ REGISTER_OUT r30 0xffffffff9e2a83c1
#_ REGISTER_OUT r31 0 #_ REGISTER_OUT r29 0
#_ REGISTER_OUT r11 0xffffffff9e2a83c1 #_ REGISTER_OUT r11 0xffffffff9e2a83c1
#_ REGISTER_OUT r12 1 #_ REGISTER_OUT r12 1