diff --git a/src/alloy/backend/ivm/ivm_intcode.cc b/src/alloy/backend/ivm/ivm_intcode.cc
index 5c5988fb4..555a904bf 100644
--- a/src/alloy/backend/ivm/ivm_intcode.cc
+++ b/src/alloy/backend/ivm/ivm_intcode.cc
@@ -2833,28 +2833,24 @@ int Translate_SHA(TranslationContext& ctx, Instr* i) {
   return DispatchToC(ctx, i, fns[i->dest->type]);
 }
 
-#define ROTL8(v, n) \
-  (uint8_t((v) << (n)) | ((v) >> (8 - (n))))
-#define ROTL16(v, n) \
-  (uint16_t((v) << (n)) | ((v) >> (16 - (n))))
-#define ROTL32(v, n) \
-  (uint32_t((v) << (n)) | ((v) >> (32 - (n))))
-#define ROTL64(v, n) \
-  (uint64_t((v) << (n)) | ((v) >> (64 - (n))))
+template<typename T>
+T ROTL(T v, int8_t sh) {
+  return (T(v) << sh) | (T(v) >> ((sizeof(T) * 8) - sh));
+}
 uint32_t IntCode_ROTATE_LEFT_I8(IntCodeState& ics, const IntCode* i) {
-  ics.rf[i->dest_reg].i8 = ROTL8(ics.rf[i->src1_reg].i8, ics.rf[i->src2_reg].i8);
+  ics.rf[i->dest_reg].i8 = ROTL<uint8_t>(ics.rf[i->src1_reg].i8, ics.rf[i->src2_reg].i8);
   return IA_NEXT;
 }
 uint32_t IntCode_ROTATE_LEFT_I16(IntCodeState& ics, const IntCode* i) {
-  ics.rf[i->dest_reg].i16 = ROTL16(ics.rf[i->src1_reg].i16, ics.rf[i->src2_reg].i8);
+  ics.rf[i->dest_reg].i16 = ROTL<uint16_t>(ics.rf[i->src1_reg].i16, ics.rf[i->src2_reg].i8);
   return IA_NEXT;
 }
 uint32_t IntCode_ROTATE_LEFT_I32(IntCodeState& ics, const IntCode* i) {
-  ics.rf[i->dest_reg].i32 = ROTL32(ics.rf[i->src1_reg].i32, ics.rf[i->src2_reg].i8);
+  ics.rf[i->dest_reg].i32 = ROTL<uint32_t>(ics.rf[i->src1_reg].i32, ics.rf[i->src2_reg].i8);
   return IA_NEXT;
 }
 uint32_t IntCode_ROTATE_LEFT_I64(IntCodeState& ics, const IntCode* i) {
-  ics.rf[i->dest_reg].i64 = ROTL64(ics.rf[i->src1_reg].i64, ics.rf[i->src2_reg].i8);
+  ics.rf[i->dest_reg].i64 = ROTL<uint64_t>(ics.rf[i->src1_reg].i64, ics.rf[i->src2_reg].i8);
   return IA_NEXT;
 }
 int Translate_ROTATE_LEFT(TranslationContext& ctx, Instr* i) {