Whoops - my arbitrarily picked GPU command # collided -_-

This commit is contained in:
Ben Vanik 2015-03-20 16:37:04 -07:00
parent 0ea8f74cf8
commit 22246cccb5
5 changed files with 38 additions and 7 deletions

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@ -836,6 +836,9 @@ bool CommandProcessor::ExecutePacketType3(RingbufferReader* reader,
case PM4_SET_CONSTANT:
result = ExecutePacketType3_SET_CONSTANT(reader, packet, count);
break;
case PM4_SET_CONSTANT2:
result = ExecutePacketType3_SET_CONSTANT2(reader, packet, count);
break;
case PM4_LOAD_ALU_CONSTANT:
result = ExecutePacketType3_LOAD_ALU_CONSTANT(reader, packet, count);
break;
@ -1198,12 +1201,12 @@ bool CommandProcessor::ExecutePacketType3_EVENT_WRITE_EXT(
address &= ~0x3;
// Let us hope we can fake this.
uint16_t extents[] = {
0 / 8, // min x
2560 / 8, // max x
0 / 8, // min y
2560 / 8, // max y
0 >> 3, // min x
2560 >> 3, // max x
0 >> 3, // min y
2560 >> 3, // max y
0, // min z
0, // max z
1, // max z
};
assert_true(endianness == xenos::Endian::k8in16);
poly::copy_and_swap_16_aligned(
@ -1324,6 +1327,17 @@ bool CommandProcessor::ExecutePacketType3_SET_CONSTANT(RingbufferReader* reader,
return true;
}
bool CommandProcessor::ExecutePacketType3_SET_CONSTANT2(
RingbufferReader* reader, uint32_t packet, uint32_t count) {
uint32_t offset_type = reader->Read();
uint32_t index = offset_type & 0xFFFF;
for (uint32_t n = 0; n < count - 1; n++, index++) {
uint32_t data = reader->Read();
WriteRegister(index, data);
}
return true;
}
bool CommandProcessor::ExecutePacketType3_LOAD_ALU_CONSTANT(
RingbufferReader* reader, uint32_t packet, uint32_t count) {
// load constants from memory

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@ -171,6 +171,8 @@ class CommandProcessor {
uint32_t count);
bool ExecutePacketType3_SET_CONSTANT(RingbufferReader* reader,
uint32_t packet, uint32_t count);
bool ExecutePacketType3_SET_CONSTANT2(RingbufferReader* reader,
uint32_t packet, uint32_t count);
bool ExecutePacketType3_LOAD_ALU_CONSTANT(RingbufferReader* reader,
uint32_t packet, uint32_t count);
bool ExecutePacketType3_SET_SHADER_CONSTANTS(RingbufferReader* reader,

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@ -326,6 +326,20 @@ bool DisasmPacketType3(const uint8_t* base_ptr, uint32_t packet,
}
break;
}
case PM4_SET_CONSTANT2: {
static const PacketTypeInfo op_info = {PacketCategory::kGeneric,
"PM4_SET_CONSTANT2"};
out_info->type_info = &op_info;
uint32_t offset_type = poly::load_and_swap<uint32_t>(ptr + 0);
uint32_t index = offset_type & 0xFFFF;
for (uint32_t n = 0; n < count - 1; n++, index++) {
uint32_t data = poly::load_and_swap<uint32_t>(ptr + 4 + n * 4);
out_info->actions.emplace_back(
PacketAction::RegisterWrite(index, data));
}
return true;
break;
}
case PM4_LOAD_ALU_CONSTANT: {
// load constants from memory
static const PacketTypeInfo op_info = {PacketCategory::kGeneric,

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@ -404,6 +404,7 @@ enum Type3Opcode {
PM4_VIZ_QUERY = 0x23, // begin/end initiator for viz query extent processing
PM4_SET_STATE = 0x25, // fetch state sub-blocks and initiate shader code DMAs
PM4_SET_CONSTANT = 0x2d, // load constant into chip and to memory
PM4_SET_CONSTANT2 = 0x55,
PM4_LOAD_ALU_CONSTANT = 0x2f, // load constants from memory
PM4_SET_SHADER_CONSTANTS = 0x56, // ?? constant values
PM4_IM_LOAD = 0x27, // load sequencer instruction memory (pointer-based)
@ -419,7 +420,7 @@ enum Type3Opcode {
PM4_CONTEXT_UPDATE = 0x5e, // updates the current context, if needed
PM4_INTERRUPT = 0x54, // generate interrupt from the command stream
PM4_XE_SWAP = 0x55, // Xenia only: VdSwap uses this to trigger a swap.
PM4_XE_SWAP = 0x64, // Xenia only: VdSwap uses this to trigger a swap.
PM4_IM_STORE = 0x2c, // copy sequencer instruction memory to system memory

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@ -396,7 +396,7 @@ SHIM_CALL VdSwap_shim(PPCContext* ppc_state, KernelState* state) {
// use this method.
memset(SHIM_MEM_ADDR(unk0), 0, 64 * 4);
auto dwords = reinterpret_cast<uint32_t*>(SHIM_MEM_ADDR(unk0));
dwords[0] = poly::byte_swap((0x03 << 30) | ((63 - 1) << 16) |
dwords[0] = poly::byte_swap((0x3 << 30) | ((63 - 1) << 16) |
(xe::gpu::xenos::PM4_XE_SWAP << 8));
dwords[1] = poly::byte_swap(frontbuffer);