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Merge pull request #408 from DrChat/vcmpbfp_rc 

vcmpbfp with Rc bit support
This commit is contained in:
Ben Vanik 2015-08-29 22:21:36 -07:00
parent b1afab5bb7 60538e7dda
commit 1631e0f234
1 changed files with 9 additions and 6 deletions
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15
src/xenia/cpu/frontend/ppc_emit_altivec.cc
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@ -580,20 +580,23 @@ XEEMITTER(vcfpuxws128, VX128_3(6, 624), VX128_3)(PPCHIRBuilder& f,
int InstrEmit_vcmpbfp_(PPCHIRBuilder& f, InstrData& i, uint32_t vd, uint32_t va, int InstrEmit_vcmpbfp_(PPCHIRBuilder& f, InstrData& i, uint32_t vd, uint32_t va,
uint32_t vb, uint32_t rc) { uint32_t vb, uint32_t rc) {
// if vA or vB are NaN, the 2 high-order bits are set (0xC0000000)
Value* va_value = f.LoadVR(va); Value* va_value = f.LoadVR(va);
Value* vb_value = f.LoadVR(vb); Value* vb_value = f.LoadVR(vb);
Value* gt = f.VectorCompareSGT(va_value, vb_value, FLOAT32_TYPE); Value* ge = f.VectorCompareSGE(va_value, vb_value, FLOAT32_TYPE);
Value* lt = Value* le =
f.Not(f.VectorCompareSGE(va_value, f.Neg(vb_value), FLOAT32_TYPE)); f.Not(f.VectorCompareSGT(va_value, f.Neg(vb_value), FLOAT32_TYPE));
Value* v = Value* v =
f.Or(f.And(gt, f.LoadConstantVec128(vec128i(0x80000000, 0x80000000, f.Or(f.And(ge, f.LoadConstantVec128(vec128i(0x80000000, 0x80000000,
0x80000000, 0x80000000))), 0x80000000, 0x80000000))),
f.And(lt, f.LoadConstantVec128(vec128i(0x40000000, 0x40000000, f.And(le, f.LoadConstantVec128(vec128i(0x40000000, 0x40000000,
0x40000000, 0x40000000)))); 0x40000000, 0x40000000))));
f.StoreVR(vd, v); f.StoreVR(vd, v);
if (rc) { if (rc) {
// CR0:4 = 0; CR0:5 = VT == 0; CR0:6 = CR0:7 = 0; // CR0:4 = 0; CR0:5 = VT == 0; CR0:6 = CR0:7 = 0;
assert_always(); // If all of the elements are within bounds, CR6[2] is set
// FIXME: Does not affect CR6[0], but the following function does.
f.UpdateCR6(f.Or(ge, le));
} }
return 0; return 0;
} }