diff --git a/src/xenia/gpu/dxbc_shader_translator.cc b/src/xenia/gpu/dxbc_shader_translator.cc index 12712a2e1..1c0f5e69d 100644 --- a/src/xenia/gpu/dxbc_shader_translator.cc +++ b/src/xenia/gpu/dxbc_shader_translator.cc @@ -67,7 +67,7 @@ void DxbcShaderTranslator::Reset() { uint32_t DxbcShaderTranslator::PushSystemTemp() { uint32_t register_index = system_temp_count_current_; - if (!uses_register_relative_addressing()) { + if (!uses_register_dynamic_addressing()) { // Guest shader registers first if they're not in x0. register_index += register_count(); } @@ -97,7 +97,7 @@ void DxbcShaderTranslator::StartVertexShader_SwapVertexIndex() { // Write to GPR 0 - either directly if not using indexable registers, or via a // system temporary register. uint32_t reg; - if (uses_register_relative_addressing()) { + if (uses_register_dynamic_addressing()) { reg = PushSystemTemp(); } else { reg = 0; @@ -304,7 +304,7 @@ void DxbcShaderTranslator::StartVertexShader_SwapVertexIndex() { ++stat_.instruction_count; ++stat_.movc_instruction_count; - if (uses_register_relative_addressing()) { + if (uses_register_dynamic_addressing()) { // Store to indexed GPR 0 in x0[0]. shader_code_.push_back(ENCODE_D3D10_SB_OPCODE_TYPE(D3D10_SB_OPCODE_MOV) | ENCODE_D3D10_SB_TOKENIZED_INSTRUCTION_LENGTH(6)); @@ -1169,7 +1169,7 @@ void DxbcShaderTranslator::WriteShaderCode() { // Temporary registers - guest general-purpose registers if not using dynamic // indexing and Xenia internal registers. stat_.temp_register_count = - (uses_register_relative_addressing() ? 0 : register_count()) + + (uses_register_dynamic_addressing() ? 0 : register_count()) + system_temp_count_max_; if (stat_.temp_register_count != 0) { shader_object_.push_back( @@ -1179,7 +1179,7 @@ void DxbcShaderTranslator::WriteShaderCode() { } // General-purpose registers if using dynamic indexing (x0). - if (uses_register_relative_addressing()) { + if (uses_register_dynamic_addressing()) { shader_object_.push_back( ENCODE_D3D10_SB_OPCODE_TYPE(D3D10_SB_OPCODE_DCL_INDEXABLE_TEMP) | ENCODE_D3D10_SB_TOKENIZED_INSTRUCTION_LENGTH(4)); diff --git a/src/xenia/gpu/shader_translator.cc b/src/xenia/gpu/shader_translator.cc index 2fffe3f0e..c15cb6ec0 100644 --- a/src/xenia/gpu/shader_translator.cc +++ b/src/xenia/gpu/shader_translator.cc @@ -58,7 +58,7 @@ void ShaderTranslator::Reset() { texture_bindings_.clear(); unique_texture_bindings_ = 0; std::memset(&constant_register_map_, 0, sizeof(constant_register_map_)); - uses_register_relative_addressing_ = false; + uses_register_dynamic_addressing_ = false; for (size_t i = 0; i < xe::countof(writes_color_targets_); ++i) { writes_color_targets_[i] = false; } @@ -267,7 +267,7 @@ void ShaderTranslator::GatherInstructionInformation( alu_vector_opcode_infos_[static_cast(op.vector_opcode())]; for (size_t i = 0; i < opcode_info.argument_count; ++i) { if (op.src_is_temp(i) && (op.src_reg(i) & 0x40)) { - uses_register_relative_addressing_ = true; + uses_register_dynamic_addressing_ = true; } } if (op.is_export()) { @@ -276,7 +276,7 @@ void ShaderTranslator::GatherInstructionInformation( } } else { if (op.is_vector_dest_relative()) { - uses_register_relative_addressing_ = true; + uses_register_dynamic_addressing_ = true; } } } @@ -285,7 +285,7 @@ void ShaderTranslator::GatherInstructionInformation( alu_scalar_opcode_infos_[static_cast(op.scalar_opcode())]; if (opcode_info.argument_count == 1 && op.src_is_temp(0) && (op.src_reg(0) & 0x40)) { - uses_register_relative_addressing_ = true; + uses_register_dynamic_addressing_ = true; } if (op.is_export()) { if (is_pixel_shader() && op.scalar_dest() <= 3) { @@ -293,7 +293,7 @@ void ShaderTranslator::GatherInstructionInformation( } } else { if (op.is_scalar_dest_relative()) { - uses_register_relative_addressing_ = true; + uses_register_dynamic_addressing_ = true; } } } @@ -317,7 +317,7 @@ void ShaderTranslator::GatherVertexFetchInformation( // Check if using dynamic register indices. if (op.is_dest_relative() || op.is_src_relative()) { - uses_register_relative_addressing_ = true; + uses_register_dynamic_addressing_ = true; } // Try to allocate an attribute on an existing binding. @@ -356,7 +356,7 @@ void ShaderTranslator::GatherTextureFetchInformation( const TextureFetchInstruction& op) { // Check if using dynamic register indices. if (op.is_dest_relative() || op.is_src_relative()) { - uses_register_relative_addressing_ = true; + uses_register_dynamic_addressing_ = true; } switch (op.opcode()) { diff --git a/src/xenia/gpu/shader_translator.h b/src/xenia/gpu/shader_translator.h index f97370ad5..8a36d0502 100644 --- a/src/xenia/gpu/shader_translator.h +++ b/src/xenia/gpu/shader_translator.h @@ -47,8 +47,8 @@ class ShaderTranslator { bool is_pixel_shader() const { return shader_type_ == ShaderType::kPixel; } // True if the current shader addresses general-purpose registers with dynamic // indices. - bool uses_register_relative_addressing() const { - return uses_register_relative_addressing_; + bool uses_register_dynamic_addressing() const { + return uses_register_dynamic_addressing_; } // A list of all vertex bindings, populated before translation occurs. const std::vector& vertex_bindings() const { @@ -220,7 +220,7 @@ class ShaderTranslator { uint32_t unique_texture_bindings_ = 0; Shader::ConstantRegisterMap constant_register_map_ = {0}; - bool uses_register_relative_addressing_ = false; + bool uses_register_dynamic_addressing_ = false; bool writes_color_targets_[4] = {false, false, false, false}; static const AluOpcodeInfo alu_vector_opcode_infos_[0x20];