[CPU] Added constant propagation pass for: OPCODE_AND_NOT
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@ -2667,34 +2667,28 @@ EMITTER_OPCODE_TABLE(OPCODE_AND, AND_I8, AND_I16, AND_I32, AND_I64, AND_V128);
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template <typename SEQ, typename REG, typename ARGS>
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template <typename SEQ, typename REG, typename ARGS>
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void EmitAndNotXX(X64Emitter& e, const ARGS& i) {
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void EmitAndNotXX(X64Emitter& e, const ARGS& i) {
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if (i.src1.is_constant) {
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if (i.src1.is_constant) {
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if (i.src2.is_constant) {
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// src1 constant.
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// Both constants.
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// `and` instruction only supports up to 32-bit immediate constants
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e.mov(i.dest, i.src1.constant() & ~i.src2.constant());
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// 64-bit constants will need a temp register
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} else {
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if (i.dest.reg().getBit() == 64) {
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// src1 constant.
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auto temp = GetTempReg<typename decltype(i.src1)::reg_type>(e);
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e.mov(temp, i.src1.constant());
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// `and` instruction only supports up to 32-bit immediate constants
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if (e.IsFeatureEnabled(kX64EmitBMI1)) {
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// 64-bit constants will need a temp register
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if (i.dest.reg().getBit() == 64) {
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if (i.dest.reg().getBit() == 64) {
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e.andn(i.dest.reg().cvt64(), i.src2.reg().cvt64(), temp.cvt64());
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auto temp = GetTempReg<typename decltype(i.src1)::reg_type>(e);
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e.mov(temp, i.src1.constant());
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if (e.IsFeatureEnabled(kX64EmitBMI1)) {
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if (i.dest.reg().getBit() == 64) {
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e.andn(i.dest.reg().cvt64(), i.src2.reg().cvt64(), temp.cvt64());
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} else {
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e.andn(i.dest.reg().cvt32(), i.src2.reg().cvt32(), temp.cvt32());
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}
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} else {
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} else {
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e.mov(i.dest, i.src2);
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e.andn(i.dest.reg().cvt32(), i.src2.reg().cvt32(), temp.cvt32());
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e.not_(i.dest);
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e.and_(i.dest, temp);
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}
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}
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} else {
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} else {
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e.mov(i.dest, i.src2);
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e.mov(i.dest, i.src2);
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e.not_(i.dest);
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e.not_(i.dest);
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e.and_(i.dest, uint32_t(i.src1.constant()));
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e.and_(i.dest, temp);
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}
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}
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} else {
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e.mov(i.dest, i.src2);
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e.not_(i.dest);
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e.and_(i.dest, uint32_t(i.src1.constant()));
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}
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}
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} else if (i.src2.is_constant) {
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} else if (i.src2.is_constant) {
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// src2 constant.
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// src2 constant.
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@ -648,6 +648,14 @@ bool ConstantPropagationPass::Run(HIRBuilder* builder, bool& result) {
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result = true;
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result = true;
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}
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}
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break;
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break;
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case OPCODE_AND_NOT:
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if (i->src1.value->IsConstant() && i->src2.value->IsConstant()) {
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v->set_from(i->src1.value);
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v->AndNot(i->src2.value);
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i->Remove();
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result = true;
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}
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break;
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case OPCODE_OR:
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case OPCODE_OR:
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if (i->src1.value->IsConstant() && i->src2.value->IsConstant()) {
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if (i->src1.value->IsConstant() && i->src2.value->IsConstant()) {
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v->set_from(i->src1.value);
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v->set_from(i->src1.value);
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@ -750,6 +750,13 @@ void Value::Not() {
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}
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}
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}
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}
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void Value::AndNot(Value* other) {
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assert_true(type == other->type);
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Value second = Value(*other);
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second.Not();
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And(&second);
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}
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void Value::Shl(Value* other) {
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void Value::Shl(Value* other) {
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assert_true(other->type == INT8_TYPE);
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assert_true(other->type == INT8_TYPE);
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switch (type) {
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switch (type) {
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@ -516,6 +516,7 @@ class Value {
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void Or(Value* other);
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void Or(Value* other);
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void Xor(Value* other);
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void Xor(Value* other);
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void Not();
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void Not();
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void AndNot(Value* other);
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void Shl(Value* other);
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void Shl(Value* other);
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void Shr(Value* other);
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void Shr(Value* other);
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void Sha(Value* other);
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void Sha(Value* other);
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