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Supporting const src1 mul_hi.

This commit is contained in:
Ben Vanik 2015-05-13 00:19:07 -07:00
parent 6fd7e35deb
commit 0d3e79ad2c
22 changed files with 258 additions and 68 deletions
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24
src/xenia/cpu/backend/x64/x64_sequences.cc
View File

@ -3299,7 +3299,11 @@ EMITTER(MUL_HI_I8, MATCH(I<OPCODE_MUL_HI, I8<>, I8<>, I8<>>)) {
}
}
} else {
e.mov(e.al, i.src1);
if (i.src1.is_constant) {
e.mov(e.al, i.src1.constant());
} else {
e.mov(e.al, i.src1);
}
if (i.src2.is_constant) {
e.mov(e.al, i.src2.constant());
e.imul(e.al);
@ -3339,7 +3343,11 @@ EMITTER(MUL_HI_I16, MATCH(I<OPCODE_MUL_HI, I16<>, I16<>, I16<>>)) {
}
}
} else {
e.mov(e.ax, i.src1);
if (i.src1.is_constant) {
e.mov(e.ax, i.src1.constant());
} else {
e.mov(e.ax, i.src1);
}
if (i.src2.is_constant) {
e.mov(e.dx, i.src2.constant());
e.imul(e.dx);
@ -3384,7 +3392,11 @@ EMITTER(MUL_HI_I32, MATCH(I<OPCODE_MUL_HI, I32<>, I32<>, I32<>>)) {
}
}
} else {
e.mov(e.eax, i.src1);
if (i.src1.is_constant) {
e.mov(e.eax, i.src1.constant());
} else {
e.mov(e.eax, i.src1);
}
if (i.src2.is_constant) {
e.mov(e.edx, i.src2.constant());
e.imul(e.edx);
@ -3429,7 +3441,11 @@ EMITTER(MUL_HI_I64, MATCH(I<OPCODE_MUL_HI, I64<>, I64<>, I64<>>)) {
}
}
} else {
e.mov(e.rax, i.src1);
if (i.src1.is_constant) {
e.mov(e.rax, i.src1.constant());
} else {
e.mov(e.rax, i.src1);
}
if (i.src2.is_constant) {
e.mov(e.rdx, i.src2.constant());
e.imul(e.rdx);

BIN
src/xenia/cpu/frontend/test/bin/instr_eqv.bin
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Binary file not shown.

70
src/xenia/cpu/frontend/test/bin/instr_eqv.dis
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@ -4,22 +4,70 @@ Disassembly of section .text:
100000: 7c 83 2a 38 eqv r3,r4,r5
100004: 4e 80 00 20 blr
0000000000100008 <test_eqv_2>:
100008: 7c 83 2a 38 eqv r3,r4,r5
10000c: 4e 80 00 20 blr
0000000000100010 <test_eqv_3>:
0000000000100008 <test_eqv_1_constant>:
100008: 38 80 00 00 li r4,0
10000c: 38 a0 00 01 li r5,1
100010: 7c 83 2a 38 eqv r3,r4,r5
100014: 4e 80 00 20 blr
0000000000100018 <test_eqv_4>:
0000000000100018 <test_eqv_2>:
100018: 7c 83 2a 38 eqv r3,r4,r5
10001c: 4e 80 00 20 blr
0000000000100020 <test_eqv_5>:
100020: 7c 83 2a 38 eqv r3,r4,r5
100024: 4e 80 00 20 blr
0000000000100028 <test_eqv_6>:
0000000000100020 <test_eqv_2_constant>:
100020: 38 80 ff ff li r4,-1
100024: 38 a0 00 00 li r5,0
100028: 7c 83 2a 38 eqv r3,r4,r5
10002c: 4e 80 00 20 blr
0000000000100030 <test_eqv_3>:
100030: 7c 83 2a 38 eqv r3,r4,r5
100034: 4e 80 00 20 blr
0000000000100038 <test_eqv_3_constant>:
100038: 38 80 ff ff li r4,-1
10003c: 38 a0 ff ff li r5,-1
100040: 7c 83 2a 38 eqv r3,r4,r5
100044: 4e 80 00 20 blr
0000000000100048 <test_eqv_4>:
100048: 7c 83 2a 38 eqv r3,r4,r5
10004c: 4e 80 00 20 blr
0000000000100050 <test_eqv_4_constant>:
100050: 3c 80 de ad lis r4,-8531
100054: 60 84 be ef ori r4,r4,48879
100058: 78 85 07 c6 rldicr r5,r4,32,31
10005c: 78 84 00 20 clrldi r4,r4,32
100060: 7c a4 23 78 or r4,r5,r4
100064: 7c 85 23 78 mr r5,r4
100068: 7c 83 2a 38 eqv r3,r4,r5
10006c: 4e 80 00 20 blr
0000000000100070 <test_eqv_5>:
100070: 7c 83 2a 38 eqv r3,r4,r5
100074: 4e 80 00 20 blr
0000000000100078 <test_eqv_5_constant>:
100078: 3c 80 de ad lis r4,-8531
10007c: 60 84 be ef ori r4,r4,48879
100080: 78 85 07 c6 rldicr r5,r4,32,31
100084: 78 84 00 20 clrldi r4,r4,32
100088: 7c a4 23 78 or r4,r5,r4
10008c: 38 a0 ff ff li r5,-1
100090: 7c 83 2a 38 eqv r3,r4,r5
100094: 4e 80 00 20 blr
0000000000100098 <test_eqv_6>:
100098: 7c 83 2a 38 eqv r3,r4,r5
10009c: 4e 80 00 20 blr
00000000001000a0 <test_eqv_6_constant>:
1000a0: 3c 80 de ad lis r4,-8531
1000a4: 60 84 be ef ori r4,r4,48879
1000a8: 78 85 07 c6 rldicr r5,r4,32,31
1000ac: 78 84 00 20 clrldi r4,r4,32
1000b0: 7c a4 23 78 or r4,r5,r4
1000b4: 38 a0 00 00 li r5,0
1000b8: 7c 83 2a 38 eqv r3,r4,r5
1000bc: 4e 80 00 20 blr

16
src/xenia/cpu/frontend/test/bin/instr_eqv.map
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@ -1,6 +1,12 @@
0000000000000000 t test_eqv_1
0000000000000008 t test_eqv_2
0000000000000010 t test_eqv_3
0000000000000018 t test_eqv_4
0000000000000020 t test_eqv_5
0000000000000028 t test_eqv_6
0000000000000008 t test_eqv_1_constant
0000000000000018 t test_eqv_2
0000000000000020 t test_eqv_2_constant
0000000000000030 t test_eqv_3
0000000000000038 t test_eqv_3_constant
0000000000000048 t test_eqv_4
0000000000000050 t test_eqv_4_constant
0000000000000070 t test_eqv_5
0000000000000078 t test_eqv_5_constant
0000000000000098 t test_eqv_6
00000000000000a0 t test_eqv_6_constant

BIN
src/xenia/cpu/frontend/test/bin/instr_lvexx.bin
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Binary file not shown.

58
src/xenia/cpu/frontend/test/bin/instr_lvexx.dis
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@ -4,22 +4,52 @@ Disassembly of section .text:
100000: 7c 60 20 0e lvebx v3,0,r4
100004: 4e 80 00 20 blr
0000000000100008 <test_lvebx_2>:
100008: 7c 60 20 0e lvebx v3,0,r4
10000c: 4e 80 00 20 blr
0000000000100008 <test_lvebx_1_constant>:
100008: 38 80 00 00 li r4,0
10000c: 7c 60 20 0e lvebx v3,0,r4
100010: 4e 80 00 20 blr
0000000000100010 <test_lvehx_1>:
100010: 7c 60 20 4e lvehx v3,0,r4
100014: 4e 80 00 20 blr
0000000000100014 <test_lvebx_2>:
100014: 7c 60 20 0e lvebx v3,0,r4
100018: 4e 80 00 20 blr
0000000000100018 <test_lvehx_2>:
100018: 7c 60 20 4e lvehx v3,0,r4
10001c: 4e 80 00 20 blr
0000000000100020 <test_lvewx_1>:
100020: 7c 60 20 8e lvewx v3,0,r4
000000000010001c <test_lvebx_2_constant>:
10001c: 38 80 00 04 li r4,4
100020: 7c 60 20 0e lvebx v3,0,r4
100024: 4e 80 00 20 blr
0000000000100028 <test_lvewx_2>:
100028: 7c 60 20 8e lvewx v3,0,r4
0000000000100028 <test_lvehx_1>:
100028: 7c 60 20 4e lvehx v3,0,r4
10002c: 4e 80 00 20 blr
0000000000100030 <test_lvehx_1_constant>:
100030: 38 80 00 00 li r4,0
100034: 7c 60 20 4e lvehx v3,0,r4
100038: 4e 80 00 20 blr
000000000010003c <test_lvehx_2>:
10003c: 7c 60 20 4e lvehx v3,0,r4
100040: 4e 80 00 20 blr
0000000000100044 <test_lvehx_2_constant>:
100044: 38 80 00 04 li r4,4
100048: 7c 60 20 4e lvehx v3,0,r4
10004c: 4e 80 00 20 blr
0000000000100050 <test_lvewx_1>:
100050: 7c 60 20 8e lvewx v3,0,r4
100054: 4e 80 00 20 blr
0000000000100058 <test_lvewx_1_constant>:
100058: 38 80 00 00 li r4,0
10005c: 7c 60 20 8e lvewx v3,0,r4
100060: 4e 80 00 20 blr
0000000000100064 <test_lvewx_2>:
100064: 7c 60 20 8e lvewx v3,0,r4
100068: 4e 80 00 20 blr
000000000010006c <test_lvewx_2_constant>:
10006c: 38 80 00 04 li r4,4
100070: 7c 60 20 8e lvewx v3,0,r4
100074: 4e 80 00 20 blr

16
src/xenia/cpu/frontend/test/bin/instr_lvexx.map
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@ -1,6 +1,12 @@
0000000000000000 t test_lvebx_1
0000000000000008 t test_lvebx_2
0000000000000010 t test_lvehx_1
0000000000000018 t test_lvehx_2
0000000000000020 t test_lvewx_1
0000000000000028 t test_lvewx_2
0000000000000008 t test_lvebx_1_constant
0000000000000014 t test_lvebx_2
000000000000001c t test_lvebx_2_constant
0000000000000028 t test_lvehx_1
0000000000000030 t test_lvehx_1_constant
000000000000003c t test_lvehx_2
0000000000000044 t test_lvehx_2_constant
0000000000000050 t test_lvewx_1
0000000000000058 t test_lvewx_1_constant
0000000000000064 t test_lvewx_2
000000000000006c t test_lvewx_2_constant

BIN
src/xenia/cpu/frontend/test/bin/instr_lvl.bin
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5
src/xenia/cpu/frontend/test/bin/instr_lvl.dis
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@ -3,3 +3,8 @@ Disassembly of section .text:
0000000000100000 <test_lvl_1>:
100000: 7c 64 04 0e lvlx v3,r4,r0
100004: 4e 80 00 20 blr
0000000000100008 <test_lvl_1_constant>:
100008: 38 80 10 77 li r4,4215
10000c: 7c 64 04 0e lvlx v3,r4,r0
100010: 4e 80 00 20 blr

1
src/xenia/cpu/frontend/test/bin/instr_lvl.map
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@ -1 +1,2 @@
0000000000000000 t test_lvl_1
0000000000000008 t test_lvl_1_constant

BIN
src/xenia/cpu/frontend/test/bin/instr_lvr.bin
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Binary file not shown.

6
src/xenia/cpu/frontend/test/bin/instr_lvr.dis
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@ -3,3 +3,9 @@ Disassembly of section .text:
0000000000100000 <test_lvr_1>:
100000: 7c 64 2c 4e lvrx v3,r4,r5
100004: 4e 80 00 20 blr
0000000000100008 <test_lvr_1_constant>:
100008: 38 80 10 b7 li r4,4279
10000c: 38 a0 00 10 li r5,16
100010: 7c 64 2c 4e lvrx v3,r4,r5
100014: 4e 80 00 20 blr

1
src/xenia/cpu/frontend/test/bin/instr_lvr.map
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@ -1 +1,2 @@
0000000000000000 t test_lvr_1
0000000000000008 t test_lvr_1_constant

BIN
src/xenia/cpu/frontend/test/bin/instr_lvsl.bin
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Binary file not shown.

27
src/xenia/cpu/frontend/test/bin/instr_lvsl.dis
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@ -4,10 +4,25 @@ Disassembly of section .text:
100000: 7c 64 00 0c lvsl v3,r4,r0
100004: 4e 80 00 20 blr
0000000000100008 <test_lvsl_2>:
100008: 7c 64 00 0c lvsl v3,r4,r0
10000c: 4e 80 00 20 blr
0000000000100008 <test_lvsl_1_constant>:
100008: 38 80 10 70 li r4,4208
10000c: 7c 64 00 0c lvsl v3,r4,r0
100010: 4e 80 00 20 blr
0000000000100010 <test_lvsl_3>:
100010: 7c 64 00 0c lvsl v3,r4,r0
100014: 4e 80 00 20 blr
0000000000100014 <test_lvsl_2>:
100014: 7c 64 00 0c lvsl v3,r4,r0
100018: 4e 80 00 20 blr
000000000010001c <test_lvsl_2_constant>:
10001c: 38 80 10 71 li r4,4209
100020: 7c 64 00 0c lvsl v3,r4,r0
100024: 4e 80 00 20 blr
0000000000100028 <test_lvsl_3>:
100028: 7c 64 00 0c lvsl v3,r4,r0
10002c: 4e 80 00 20 blr
0000000000100030 <test_lvsl_3_constant>:
100030: 38 80 10 7f li r4,4223
100034: 7c 64 00 0c lvsl v3,r4,r0
100038: 4e 80 00 20 blr

7
src/xenia/cpu/frontend/test/bin/instr_lvsl.map
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@ -1,3 +1,6 @@
0000000000000000 t test_lvsl_1
0000000000000008 t test_lvsl_2
0000000000000010 t test_lvsl_3
0000000000000008 t test_lvsl_1_constant
0000000000000014 t test_lvsl_2
000000000000001c t test_lvsl_2_constant
0000000000000028 t test_lvsl_3
0000000000000030 t test_lvsl_3_constant

BIN
src/xenia/cpu/frontend/test/bin/instr_lvsr.bin
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Binary file not shown.

27
src/xenia/cpu/frontend/test/bin/instr_lvsr.dis
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@ -4,10 +4,25 @@ Disassembly of section .text:
100000: 7c 64 00 4c lvsr v3,r4,r0
100004: 4e 80 00 20 blr
0000000000100008 <test_lvsr_2>:
100008: 7c 64 00 4c lvsr v3,r4,r0
10000c: 4e 80 00 20 blr
0000000000100008 <test_lvsr_1_constant>:
100008: 38 80 10 70 li r4,4208
10000c: 7c 64 00 4c lvsr v3,r4,r0
100010: 4e 80 00 20 blr
0000000000100010 <test_lvsr_3>:
100010: 7c 64 00 4c lvsr v3,r4,r0
100014: 4e 80 00 20 blr
0000000000100014 <test_lvsr_2>:
100014: 7c 64 00 4c lvsr v3,r4,r0
100018: 4e 80 00 20 blr
000000000010001c <test_lvsr_2_constant>:
10001c: 38 80 10 71 li r4,4209
100020: 7c 64 00 4c lvsr v3,r4,r0
100024: 4e 80 00 20 blr
0000000000100028 <test_lvsr_3>:
100028: 7c 64 00 4c lvsr v3,r4,r0
10002c: 4e 80 00 20 blr
0000000000100030 <test_lvsr_3_constant>:
100030: 38 80 10 7f li r4,4223
100034: 7c 64 00 4c lvsr v3,r4,r0
100038: 4e 80 00 20 blr

7
src/xenia/cpu/frontend/test/bin/instr_lvsr.map
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@ -1,3 +1,6 @@
0000000000000000 t test_lvsr_1
0000000000000008 t test_lvsr_2
0000000000000010 t test_lvsr_3
0000000000000008 t test_lvsr_1_constant
0000000000000014 t test_lvsr_2
000000000000001c t test_lvsr_2_constant
0000000000000028 t test_lvsr_3
0000000000000030 t test_lvsr_3_constant

BIN
src/xenia/cpu/frontend/test/bin/instr_mulhd.bin
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Binary file not shown.

48
src/xenia/cpu/frontend/test/bin/instr_mulhd.dis
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@ -4,18 +4,48 @@ Disassembly of section .text:
100000: 7c 64 28 92 mulhd r3,r4,r5
100004: 4e 80 00 20 blr
0000000000100008 <test_mulhd_2>:
100008: 7c 64 28 92 mulhd r3,r4,r5
10000c: 4e 80 00 20 blr
0000000000100010 <test_mulhd_3>:
0000000000100008 <test_mulhd_1_constant>:
100008: 38 80 00 01 li r4,1
10000c: 38 a0 00 00 li r5,0
100010: 7c 64 28 92 mulhd r3,r4,r5
100014: 4e 80 00 20 blr
0000000000100018 <test_mulhd_4>:
0000000000100018 <test_mulhd_2>:
100018: 7c 64 28 92 mulhd r3,r4,r5
10001c: 4e 80 00 20 blr
0000000000100020 <test_mulhd_5>:
100020: 7c 64 28 92 mulhd r3,r4,r5
100024: 4e 80 00 20 blr
0000000000100020 <test_mulhd_2_constant>:
100020: 38 80 ff ff li r4,-1
100024: 38 a0 00 01 li r5,1
100028: 7c 64 28 92 mulhd r3,r4,r5
10002c: 4e 80 00 20 blr
0000000000100030 <test_mulhd_3>:
100030: 7c 64 28 92 mulhd r3,r4,r5
100034: 4e 80 00 20 blr
0000000000100038 <test_mulhd_3_constant>:
100038: 38 80 ff ff li r4,-1
10003c: 38 a0 00 02 li r5,2
100040: 7c 64 28 92 mulhd r3,r4,r5
100044: 4e 80 00 20 blr
0000000000100048 <test_mulhd_4>:
100048: 7c 64 28 92 mulhd r3,r4,r5
10004c: 4e 80 00 20 blr
0000000000100050 <test_mulhd_4_constant>:
100050: 38 a0 00 01 li r5,1
100054: 78 a4 f8 06 rldicr r4,r5,63,0
100058: 7c 64 28 92 mulhd r3,r4,r5
10005c: 4e 80 00 20 blr
0000000000100060 <test_mulhd_5>:
100060: 7c 64 28 92 mulhd r3,r4,r5
100064: 4e 80 00 20 blr
0000000000100068 <test_mulhd_5_constant>:
100068: 38 80 ff ff li r4,-1
10006c: 38 a0 ff ff li r5,-1
100070: 7c 64 28 92 mulhd r3,r4,r5
100074: 4e 80 00 20 blr

13
src/xenia/cpu/frontend/test/bin/instr_mulhd.map
View File

@ -1,5 +1,10 @@
0000000000000000 t test_mulhd_1
0000000000000008 t test_mulhd_2
0000000000000010 t test_mulhd_3
0000000000000018 t test_mulhd_4
0000000000000020 t test_mulhd_5
0000000000000008 t test_mulhd_1_constant
0000000000000018 t test_mulhd_2
0000000000000020 t test_mulhd_2_constant
0000000000000030 t test_mulhd_3
0000000000000038 t test_mulhd_3_constant
0000000000000048 t test_mulhd_4
0000000000000050 t test_mulhd_4_constant
0000000000000060 t test_mulhd_5
0000000000000068 t test_mulhd_5_constant