From 00b79d66ff84e3c86432c0dd5a77d167505eb4ad Mon Sep 17 00:00:00 2001 From: Ben Vanik Date: Wed, 13 May 2015 18:04:33 -0700 Subject: [PATCH] Fixing sub carry flag. --- src/xenia/cpu/frontend/test/bin/instr_add.bin | Bin 56 -> 228 bytes src/xenia/cpu/frontend/test/bin/instr_add.dis | 63 +++++ src/xenia/cpu/frontend/test/bin/instr_add.map | 10 + .../cpu/frontend/test/bin/instr_cntlzd.bin | Bin 92 -> 84 bytes .../cpu/frontend/test/bin/instr_cntlzd.dis | 24 +- .../cpu/frontend/test/bin/instr_cntlzd.map | 4 +- .../cpu/frontend/test/bin/instr_cntlzw.bin | Bin 96 -> 88 bytes .../cpu/frontend/test/bin/instr_cntlzw.dis | 26 +- .../cpu/frontend/test/bin/instr_cntlzw.map | 4 +- .../cpu/frontend/test/bin/instr_mulhdu.bin | Bin 40 -> 120 bytes .../cpu/frontend/test/bin/instr_mulhdu.dis | 48 +++- .../cpu/frontend/test/bin/instr_mulhdu.map | 13 +- .../cpu/frontend/test/bin/instr_mulhw.bin | Bin 48 -> 168 bytes .../cpu/frontend/test/bin/instr_mulhw.dis | 66 ++++- .../cpu/frontend/test/bin/instr_mulhw.map | 16 +- .../cpu/frontend/test/bin/instr_mulhwu.bin | Bin 48 -> 168 bytes .../cpu/frontend/test/bin/instr_mulhwu.dis | 66 ++++- .../cpu/frontend/test/bin/instr_mulhwu.map | 16 +- .../cpu/frontend/test/bin/instr_mulld.bin | Bin 64 -> 192 bytes .../cpu/frontend/test/bin/instr_mulld.dis | 78 ++++-- .../cpu/frontend/test/bin/instr_mulld.map | 22 +- .../cpu/frontend/test/bin/instr_mulli.bin | Bin 64 -> 160 bytes .../cpu/frontend/test/bin/instr_mulli.dis | 78 ++++-- .../cpu/frontend/test/bin/instr_mulli.map | 22 +- .../cpu/frontend/test/bin/instr_mullw.bin | Bin 88 -> 276 bytes .../cpu/frontend/test/bin/instr_mullw.dis | 111 ++++++-- .../cpu/frontend/test/bin/instr_mullw.map | 31 ++- src/xenia/cpu/frontend/test/bin/instr_neg.bin | Bin 24 -> 68 bytes src/xenia/cpu/frontend/test/bin/instr_neg.dis | 27 +- src/xenia/cpu/frontend/test/bin/instr_neg.map | 7 +- src/xenia/cpu/frontend/test/bin/instr_nor.bin | Bin 20 -> 48 bytes src/xenia/cpu/frontend/test/bin/instr_nor.dis | 11 + src/xenia/cpu/frontend/test/bin/instr_nor.map | 2 + src/xenia/cpu/frontend/test/bin/instr_ori.bin | Bin 16 -> 64 bytes src/xenia/cpu/frontend/test/bin/instr_ori.dis | 22 +- src/xenia/cpu/frontend/test/bin/instr_ori.map | 4 +- .../cpu/frontend/test/bin/instr_rldicl.bin | Bin 128 -> 640 bytes .../cpu/frontend/test/bin/instr_rldicl.dis | 242 ++++++++++++++---- .../cpu/frontend/test/bin/instr_rldicl.map | 40 ++- .../cpu/frontend/test/bin/instr_rldicr.bin | Bin 120 -> 620 bytes .../cpu/frontend/test/bin/instr_rldicr.dis | 241 +++++++++++++---- .../cpu/frontend/test/bin/instr_rldicr.map | 37 ++- .../cpu/frontend/test/bin/instr_rlwimi.bin | Bin 8 -> 72 bytes .../cpu/frontend/test/bin/instr_rlwimi.dis | 18 ++ .../cpu/frontend/test/bin/instr_rlwimi.map | 1 + .../cpu/frontend/test/bin/instr_rlwinm.bin | Bin 80 -> 244 bytes .../cpu/frontend/test/bin/instr_rlwinm.dis | 115 +++++++-- .../cpu/frontend/test/bin/instr_rlwinm.map | 28 +- .../cpu/frontend/test/bin/instr_rlwnm.bin | Bin 80 -> 288 bytes .../cpu/frontend/test/bin/instr_rlwnm.dis | 128 +++++++-- .../cpu/frontend/test/bin/instr_rlwnm.map | 28 +- src/xenia/cpu/frontend/test/bin/instr_sld.bin | Bin 56 -> 168 bytes src/xenia/cpu/frontend/test/bin/instr_sld.dis | 66 ++++- src/xenia/cpu/frontend/test/bin/instr_sld.map | 19 +- src/xenia/cpu/frontend/test/bin/instr_slw.bin | Bin 72 -> 216 bytes src/xenia/cpu/frontend/test/bin/instr_slw.dis | 88 +++++-- src/xenia/cpu/frontend/test/bin/instr_slw.map | 25 +- .../cpu/frontend/test/bin/instr_srad.bin | Bin 84 -> 224 bytes .../cpu/frontend/test/bin/instr_srad.dis | 97 +++++-- .../cpu/frontend/test/bin/instr_srad.map | 19 +- .../cpu/frontend/test/bin/instr_sradi.bin | Bin 60 -> 140 bytes .../cpu/frontend/test/bin/instr_sradi.dis | 62 +++-- .../cpu/frontend/test/bin/instr_sradi.map | 13 +- .../cpu/frontend/test/bin/instr_sraw.bin | Bin 108 -> 288 bytes .../cpu/frontend/test/bin/instr_sraw.dis | 119 +++++++-- .../cpu/frontend/test/bin/instr_sraw.map | 25 +- .../cpu/frontend/test/bin/instr_srawi.bin | Bin 60 -> 140 bytes .../cpu/frontend/test/bin/instr_srawi.dis | 62 +++-- .../cpu/frontend/test/bin/instr_srawi.map | 13 +- src/xenia/cpu/frontend/test/bin/instr_srd.bin | Bin 56 -> 168 bytes src/xenia/cpu/frontend/test/bin/instr_srd.dis | 66 ++++- src/xenia/cpu/frontend/test/bin/instr_srd.map | 19 +- src/xenia/cpu/frontend/test/bin/instr_srw.bin | Bin 72 -> 216 bytes src/xenia/cpu/frontend/test/bin/instr_srw.dis | 88 +++++-- src/xenia/cpu/frontend/test/bin/instr_srw.map | 25 +- .../cpu/frontend/test/bin/instr_stvew.bin | Bin 32 -> 80 bytes .../cpu/frontend/test/bin/instr_stvew.dis | 38 ++- .../cpu/frontend/test/bin/instr_stvew.map | 10 +- .../cpu/frontend/test/bin/instr_stvl.bin | Bin 16 -> 40 bytes .../cpu/frontend/test/bin/instr_stvl.dis | 16 +- .../cpu/frontend/test/bin/instr_stvl.map | 4 +- .../cpu/frontend/test/bin/instr_stvr.bin | Bin 16 -> 44 bytes .../cpu/frontend/test/bin/instr_stvr.dis | 17 +- .../cpu/frontend/test/bin/instr_stvr.map | 4 +- .../cpu/frontend/test/bin/instr_subf.bin | Bin 40 -> 128 bytes .../cpu/frontend/test/bin/instr_subf.dis | 52 +++- .../cpu/frontend/test/bin/instr_subf.map | 13 +- .../cpu/frontend/test/bin/instr_subfc.bin | Bin 60 -> 168 bytes .../cpu/frontend/test/bin/instr_subfc.dis | 69 +++-- .../cpu/frontend/test/bin/instr_subfc.map | 13 +- .../cpu/frontend/test/bin/instr_subfe.bin | Bin 60 -> 168 bytes .../cpu/frontend/test/bin/instr_subfe.dis | 69 +++-- .../cpu/frontend/test/bin/instr_subfe.map | 13 +- .../cpu/frontend/test/bin/instr_subfic.bin | Bin 72 -> 176 bytes .../cpu/frontend/test/bin/instr_subfic.dis | 78 ++++-- .../cpu/frontend/test/bin/instr_subfic.map | 16 +- .../cpu/frontend/test/bin/instr_subfme.bin | Bin 176 -> 392 bytes .../cpu/frontend/test/bin/instr_subfme.dis | 160 ++++++++---- .../cpu/frontend/test/bin/instr_subfme.map | 22 +- .../cpu/frontend/test/bin/instr_subfze.bin | Bin 176 -> 392 bytes .../cpu/frontend/test/bin/instr_subfze.dis | 160 ++++++++---- .../cpu/frontend/test/bin/instr_subfze.map | 22 +- src/xenia/cpu/hir/value.cc | 14 +- 103 files changed, 2491 insertions(+), 754 deletions(-) diff --git a/src/xenia/cpu/frontend/test/bin/instr_add.bin b/src/xenia/cpu/frontend/test/bin/instr_add.bin index ceb82a07180de9fcc60b970a3b7bb25f84b37a27..5bdd9dc6d12ff3e931004da2ee7ca542e7ca16a6 100644 GIT binary patch literal 228 zcmb+TpXw$&bC1{ i11^rN#)9Ghf4Ccv^kS-EU_=%}W&_PQ2Q=e3vKRodK};?H delta 5 McmaFDXfeS800w;l<^TWy diff --git a/src/xenia/cpu/frontend/test/bin/instr_add.dis b/src/xenia/cpu/frontend/test/bin/instr_add.dis index f2a41f40c..b763e8f75 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_add.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_add.dis @@ -21,3 +21,66 @@ Disassembly of section .text: 10002c: 7b 39 04 20 clrldi r25,r25,48 100030: 7d 60 ca 14 add r11,r0,r25 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 7d 65 ca 15 add. r11,r5,r25 + 10003c: 7d 80 00 26 mfcr r12 + 100040: 4e 80 00 20 blr + +0000000000100044 : + 100044: 3c a0 00 10 lis r5,16 + 100048: 3b 20 ff ff li r25,-1 + 10004c: 7b 39 04 20 clrldi r25,r25,48 + 100050: 7d 65 ca 15 add. r11,r5,r25 + 100054: 7d 80 00 26 mfcr r12 + 100058: 4e 80 00 20 blr + +000000000010005c : + 10005c: 7d 60 ca 15 add. r11,r0,r25 + 100060: 7d 80 00 26 mfcr r12 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 3c 00 00 10 lis r0,16 + 10006c: 3b 20 ff ff li r25,-1 + 100070: 7b 39 04 20 clrldi r25,r25,48 + 100074: 7d 60 ca 15 add. r11,r0,r25 + 100078: 7d 80 00 26 mfcr r12 + 10007c: 4e 80 00 20 blr + +0000000000100080 : + 100080: 7d 60 ca 15 add. r11,r0,r25 + 100084: 7d 80 00 26 mfcr r12 + 100088: 4e 80 00 20 blr + +000000000010008c : + 10008c: 38 00 ff ff li r0,-1 + 100090: 3b 20 ff ff li r25,-1 + 100094: 7b 39 04 20 clrldi r25,r25,48 + 100098: 7d 60 ca 15 add. r11,r0,r25 + 10009c: 7d 80 00 26 mfcr r12 + 1000a0: 4e 80 00 20 blr + +00000000001000a4 : + 1000a4: 7d 60 ca 15 add. r11,r0,r25 + 1000a8: 7d 80 00 26 mfcr r12 + 1000ac: 4e 80 00 20 blr + +00000000001000b0 : + 1000b0: 38 00 ff ff li r0,-1 + 1000b4: 3b 20 00 01 li r25,1 + 1000b8: 7d 60 ca 15 add. r11,r0,r25 + 1000bc: 7d 80 00 26 mfcr r12 + 1000c0: 4e 80 00 20 blr + +00000000001000c4 : + 1000c4: 7d 60 ca 15 add. r11,r0,r25 + 1000c8: 7d 80 00 26 mfcr r12 + 1000cc: 4e 80 00 20 blr + +00000000001000d0 : + 1000d0: 38 00 ff ce li r0,-50 + 1000d4: 3b 20 ff e7 li r25,-25 + 1000d8: 7d 60 ca 15 add. r11,r0,r25 + 1000dc: 7d 80 00 26 mfcr r12 + 1000e0: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_add.map b/src/xenia/cpu/frontend/test/bin/instr_add.map index 9bc31b7e2..0e96bffac 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_add.map +++ b/src/xenia/cpu/frontend/test/bin/instr_add.map @@ -2,3 +2,13 @@ 0000000000000008 t test_add_1_constant 000000000000001c t test_add_2 0000000000000024 t test_add_2_constant +0000000000000038 t test_add_cr_1 +0000000000000044 t test_add_cr_1_constant +000000000000005c t test_add_cr_2 +0000000000000068 t test_add_cr_2_constant +0000000000000080 t test_add_cr_3 +000000000000008c t test_add_cr_3_constant +00000000000000a4 t test_add_cr_4 +00000000000000b0 t test_add_cr_4_constant +00000000000000c4 t test_add_cr_5 +00000000000000d0 t test_add_cr_5_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_cntlzd.bin b/src/xenia/cpu/frontend/test/bin/instr_cntlzd.bin index 95c1cb8ee8df9f63f215031c971b394a8b7d10ba..d4b938a275434fb3c43aa784a990a5afdc72c9b7 100644 GIT binary patch delta 39 icmazEnP8;!|9{Ogh7!L91_c;xvEcvzilslCV0-{eoe)d_ delta 47 mcmWHEnP8;Fz)-VP<44Uhh7!L91_c;xu>c}ovGj)%Obh^t@etYo diff --git a/src/xenia/cpu/frontend/test/bin/instr_cntlzd.dis b/src/xenia/cpu/frontend/test/bin/instr_cntlzd.dis index 1259ddfa3..f00dffae1 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_cntlzd.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_cntlzd.dis @@ -23,18 +23,16 @@ Disassembly of section .text: 10002c: 4e 80 00 20 blr 0000000000100030 : - 100030: 38 a0 00 00 li r5,0 - 100034: 7c a5 28 f8 not r5,r5 - 100038: 7c a6 00 74 cntlzd r6,r5 - 10003c: 4e 80 00 20 blr + 100030: 38 a0 ff ff li r5,-1 + 100034: 7c a6 00 74 cntlzd r6,r5 + 100038: 4e 80 00 20 blr -0000000000100040 : - 100040: 7c a6 00 74 cntlzd r6,r5 - 100044: 4e 80 00 20 blr +000000000010003c : + 10003c: 7c a6 00 74 cntlzd r6,r5 + 100040: 4e 80 00 20 blr -0000000000100048 : - 100048: 38 a0 00 00 li r5,0 - 10004c: 7c a5 28 f8 not r5,r5 - 100050: 78 a5 f8 42 rldicl r5,r5,63,1 - 100054: 7c a6 00 74 cntlzd r6,r5 - 100058: 4e 80 00 20 blr +0000000000100044 : + 100044: 38 a0 ff ff li r5,-1 + 100048: 78 a5 f8 42 rldicl r5,r5,63,1 + 10004c: 7c a6 00 74 cntlzd r6,r5 + 100050: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_cntlzd.map b/src/xenia/cpu/frontend/test/bin/instr_cntlzd.map index 68ddb40bd..f2817f50d 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_cntlzd.map +++ b/src/xenia/cpu/frontend/test/bin/instr_cntlzd.map @@ -4,5 +4,5 @@ 000000000000001c t test_cntlzd_2_constant 0000000000000028 t test_cntlzd_3 0000000000000030 t test_cntlzd_3_constant -0000000000000040 t test_cntlzd_4 -0000000000000048 t test_cntlzd_4_constant +000000000000003c t test_cntlzd_4 +0000000000000044 t test_cntlzd_4_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_cntlzw.bin b/src/xenia/cpu/frontend/test/bin/instr_cntlzw.bin index 53b8558e28ac7a01e78bb451e8c604387120d23b..aac45e6a6c8997d3e23037374bbce4cf02e1e700 100644 GIT binary patch delta 43 kcmYd@m|&##|9{9*2D_SN3?_aJ3<@yXVgX3}M;(k00C?gM=Kufz literal 96 wcmb: - 100030: 38 a0 00 00 li r5,0 - 100034: 7c a5 28 f8 not r5,r5 - 100038: 54 a5 00 3e rotlwi r5,r5,0 - 10003c: 7c a6 00 34 cntlzw r6,r5 - 100040: 4e 80 00 20 blr + 100030: 38 a0 ff ff li r5,-1 + 100034: 54 a5 00 3e rotlwi r5,r5,0 + 100038: 7c a6 00 34 cntlzw r6,r5 + 10003c: 4e 80 00 20 blr -0000000000100044 : - 100044: 7c a6 00 34 cntlzw r6,r5 - 100048: 4e 80 00 20 blr +0000000000100040 : + 100040: 7c a6 00 34 cntlzw r6,r5 + 100044: 4e 80 00 20 blr -000000000010004c : - 10004c: 38 a0 00 00 li r5,0 - 100050: 7c a5 28 f8 not r5,r5 - 100054: 54 a5 f8 7e rlwinm r5,r5,31,1,31 - 100058: 7c a6 00 34 cntlzw r6,r5 - 10005c: 4e 80 00 20 blr +0000000000100048 : + 100048: 38 a0 ff ff li r5,-1 + 10004c: 54 a5 f8 7e rlwinm r5,r5,31,1,31 + 100050: 7c a6 00 34 cntlzw r6,r5 + 100054: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_cntlzw.map b/src/xenia/cpu/frontend/test/bin/instr_cntlzw.map index d4d7b9048..884445add 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_cntlzw.map +++ b/src/xenia/cpu/frontend/test/bin/instr_cntlzw.map @@ -4,5 +4,5 @@ 000000000000001c t test_cntlzw_2_constant 0000000000000028 t test_cntlzw_3 0000000000000030 t test_cntlzw_3_constant -0000000000000044 t test_cntlzw_4 -000000000000004c t test_cntlzw_4_constant +0000000000000040 t test_cntlzw_4 +0000000000000048 t test_cntlzw_4_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_mulhdu.bin b/src/xenia/cpu/frontend/test/bin/instr_mulhdu.bin index 9710b2b7805469776e6a05ea43193487077ae410..96750c05414bfad39bcbdaab32a88d2d3059c7f1 100644 GIT binary patch literal 120 zcmblMdMnly9 I{}1B>06%{vfB*mh literal 40 Scmb: - 100008: 7c 64 28 12 mulhdu r3,r4,r5 - 10000c: 4e 80 00 20 blr - -0000000000100010 : +0000000000100008 : + 100008: 38 80 00 01 li r4,1 + 10000c: 38 a0 00 00 li r5,0 100010: 7c 64 28 12 mulhdu r3,r4,r5 100014: 4e 80 00 20 blr -0000000000100018 : +0000000000100018 : 100018: 7c 64 28 12 mulhdu r3,r4,r5 10001c: 4e 80 00 20 blr -0000000000100020 : - 100020: 7c 64 28 12 mulhdu r3,r4,r5 - 100024: 4e 80 00 20 blr +0000000000100020 : + 100020: 38 80 ff ff li r4,-1 + 100024: 38 a0 00 01 li r5,1 + 100028: 7c 64 28 12 mulhdu r3,r4,r5 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c 64 28 12 mulhdu r3,r4,r5 + 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 38 80 ff ff li r4,-1 + 10003c: 38 a0 00 02 li r5,2 + 100040: 7c 64 28 12 mulhdu r3,r4,r5 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c 64 28 12 mulhdu r3,r4,r5 + 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 38 a0 00 01 li r5,1 + 100054: 78 a4 f8 06 rldicr r4,r5,63,0 + 100058: 7c 64 28 12 mulhdu r3,r4,r5 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 7c 64 28 12 mulhdu r3,r4,r5 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 38 80 ff ff li r4,-1 + 10006c: 38 a0 ff ff li r5,-1 + 100070: 7c 64 28 12 mulhdu r3,r4,r5 + 100074: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_mulhdu.map b/src/xenia/cpu/frontend/test/bin/instr_mulhdu.map index 52d4039b0..e8f67a2d6 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_mulhdu.map +++ b/src/xenia/cpu/frontend/test/bin/instr_mulhdu.map @@ -1,5 +1,10 @@ 0000000000000000 t test_mulhdu_1 -0000000000000008 t test_mulhdu_2 -0000000000000010 t test_mulhdu_3 -0000000000000018 t test_mulhdu_4 -0000000000000020 t test_mulhdu_5 +0000000000000008 t test_mulhdu_1_constant +0000000000000018 t test_mulhdu_2 +0000000000000020 t test_mulhdu_2_constant +0000000000000030 t test_mulhdu_3 +0000000000000038 t test_mulhdu_3_constant +0000000000000048 t test_mulhdu_4 +0000000000000050 t test_mulhdu_4_constant +0000000000000060 t test_mulhdu_5 +0000000000000068 t test_mulhdu_5_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_mulhw.bin b/src/xenia/cpu/frontend/test/bin/instr_mulhw.bin index 1a38c4ccde837bfd61b85ebca917c6e0bc52d52d..dfb1239c5c6552ceb31829f20754494ac44fb1b1 100644 GIT binary patch literal 168 zcmb: - 100008: 7c 64 28 96 mulhw r3,r4,r5 - 10000c: 4e 80 00 20 blr - -0000000000100010 : +0000000000100008 : + 100008: 38 80 00 01 li r4,1 + 10000c: 38 a0 00 00 li r5,0 100010: 7c 64 28 96 mulhw r3,r4,r5 100014: 4e 80 00 20 blr -0000000000100018 : +0000000000100018 : 100018: 7c 64 28 96 mulhw r3,r4,r5 10001c: 4e 80 00 20 blr -0000000000100020 : - 100020: 7c 64 28 96 mulhw r3,r4,r5 - 100024: 4e 80 00 20 blr +0000000000100020 : + 100020: 38 80 ff ff li r4,-1 + 100024: 78 84 00 20 clrldi r4,r4,32 + 100028: 38 a0 00 01 li r5,1 + 10002c: 7c 64 28 96 mulhw r3,r4,r5 + 100030: 4e 80 00 20 blr -0000000000100028 : - 100028: 7c 64 28 96 mulhw r3,r4,r5 - 10002c: 4e 80 00 20 blr +0000000000100034 : + 100034: 7c 64 28 96 mulhw r3,r4,r5 + 100038: 4e 80 00 20 blr + +000000000010003c : + 10003c: 38 80 ff ff li r4,-1 + 100040: 78 84 07 c0 clrldi r4,r4,31 + 100044: 38 a0 00 01 li r5,1 + 100048: 7c 64 28 96 mulhw r3,r4,r5 + 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 7c 64 28 96 mulhw r3,r4,r5 + 100054: 4e 80 00 20 blr + +0000000000100058 : + 100058: 38 80 ff ff li r4,-1 + 10005c: 78 84 00 60 clrldi r4,r4,33 + 100060: 38 a0 00 01 li r5,1 + 100064: 78 a5 f8 06 rldicr r5,r5,63,0 + 100068: 7c 84 2b 78 or r4,r4,r5 + 10006c: 38 a0 00 01 li r5,1 + 100070: 7c 64 28 96 mulhw r3,r4,r5 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 7c 64 28 96 mulhw r3,r4,r5 + 10007c: 4e 80 00 20 blr + +0000000000100080 : + 100080: 38 80 ff ff li r4,-1 + 100084: 38 a0 00 01 li r5,1 + 100088: 7c 64 28 96 mulhw r3,r4,r5 + 10008c: 4e 80 00 20 blr + +0000000000100090 : + 100090: 7c 64 28 96 mulhw r3,r4,r5 + 100094: 4e 80 00 20 blr + +0000000000100098 : + 100098: 38 80 ff ff li r4,-1 + 10009c: 38 a0 ff ff li r5,-1 + 1000a0: 7c 64 28 96 mulhw r3,r4,r5 + 1000a4: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_mulhw.map b/src/xenia/cpu/frontend/test/bin/instr_mulhw.map index 5699dda49..190836aa5 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_mulhw.map +++ b/src/xenia/cpu/frontend/test/bin/instr_mulhw.map @@ -1,6 +1,12 @@ 0000000000000000 t test_mulhw_1 -0000000000000008 t test_mulhw_2 -0000000000000010 t test_mulhw_3 -0000000000000018 t test_mulhw_4 -0000000000000020 t test_mulhw_5 -0000000000000028 t test_mulhw_6 +0000000000000008 t test_mulhw_1_constant +0000000000000018 t test_mulhw_2 +0000000000000020 t test_mulhw_2_constant +0000000000000034 t test_mulhw_3 +000000000000003c t test_mulhw_3_constant +0000000000000050 t test_mulhw_4 +0000000000000058 t test_mulhw_4_constant +0000000000000078 t test_mulhw_5 +0000000000000080 t test_mulhw_5_constant +0000000000000090 t test_mulhw_6 +0000000000000098 t test_mulhw_6_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_mulhwu.bin b/src/xenia/cpu/frontend/test/bin/instr_mulhwu.bin index db45968054ba49ccef032b76df19c28716fd40f9..7327737f373769d204007db768949552c8518d62 100644 GIT binary patch literal 168 zcmb: - 100008: 7c 64 28 16 mulhwu r3,r4,r5 - 10000c: 4e 80 00 20 blr - -0000000000100010 : +0000000000100008 : + 100008: 38 80 00 01 li r4,1 + 10000c: 38 a0 00 00 li r5,0 100010: 7c 64 28 16 mulhwu r3,r4,r5 100014: 4e 80 00 20 blr -0000000000100018 : +0000000000100018 : 100018: 7c 64 28 16 mulhwu r3,r4,r5 10001c: 4e 80 00 20 blr -0000000000100020 : - 100020: 7c 64 28 16 mulhwu r3,r4,r5 - 100024: 4e 80 00 20 blr +0000000000100020 : + 100020: 38 80 ff ff li r4,-1 + 100024: 78 84 00 20 clrldi r4,r4,32 + 100028: 38 a0 00 01 li r5,1 + 10002c: 7c 64 28 16 mulhwu r3,r4,r5 + 100030: 4e 80 00 20 blr -0000000000100028 : - 100028: 7c 64 28 16 mulhwu r3,r4,r5 - 10002c: 4e 80 00 20 blr +0000000000100034 : + 100034: 7c 64 28 16 mulhwu r3,r4,r5 + 100038: 4e 80 00 20 blr + +000000000010003c : + 10003c: 38 80 ff ff li r4,-1 + 100040: 78 84 07 c0 clrldi r4,r4,31 + 100044: 38 a0 00 01 li r5,1 + 100048: 7c 64 28 16 mulhwu r3,r4,r5 + 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 7c 64 28 16 mulhwu r3,r4,r5 + 100054: 4e 80 00 20 blr + +0000000000100058 : + 100058: 38 80 ff ff li r4,-1 + 10005c: 78 84 00 60 clrldi r4,r4,33 + 100060: 38 a0 00 01 li r5,1 + 100064: 78 a5 f8 06 rldicr r5,r5,63,0 + 100068: 7c 84 2b 78 or r4,r4,r5 + 10006c: 38 a0 00 01 li r5,1 + 100070: 7c 64 28 16 mulhwu r3,r4,r5 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 7c 64 28 16 mulhwu r3,r4,r5 + 10007c: 4e 80 00 20 blr + +0000000000100080 : + 100080: 38 80 ff ff li r4,-1 + 100084: 38 a0 00 01 li r5,1 + 100088: 7c 64 28 16 mulhwu r3,r4,r5 + 10008c: 4e 80 00 20 blr + +0000000000100090 : + 100090: 7c 64 28 16 mulhwu r3,r4,r5 + 100094: 4e 80 00 20 blr + +0000000000100098 : + 100098: 38 80 ff ff li r4,-1 + 10009c: 38 a0 ff ff li r5,-1 + 1000a0: 7c 64 28 16 mulhwu r3,r4,r5 + 1000a4: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_mulhwu.map b/src/xenia/cpu/frontend/test/bin/instr_mulhwu.map index 2c8ddc055..1437d4347 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_mulhwu.map +++ b/src/xenia/cpu/frontend/test/bin/instr_mulhwu.map @@ -1,6 +1,12 @@ 0000000000000000 t test_mulhwu_1 -0000000000000008 t test_mulhwu_2 -0000000000000010 t test_mulhwu_3 -0000000000000018 t test_mulhwu_4 -0000000000000020 t test_mulhwu_5 -0000000000000028 t test_mulhwu_6 +0000000000000008 t test_mulhwu_1_constant +0000000000000018 t test_mulhwu_2 +0000000000000020 t test_mulhwu_2_constant +0000000000000034 t test_mulhwu_3 +000000000000003c t test_mulhwu_3_constant +0000000000000050 t test_mulhwu_4 +0000000000000058 t test_mulhwu_4_constant +0000000000000078 t test_mulhwu_5 +0000000000000080 t test_mulhwu_5_constant +0000000000000090 t test_mulhwu_6 +0000000000000098 t test_mulhwu_6_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_mulld.bin b/src/xenia/cpu/frontend/test/bin/instr_mulld.bin index e93d7cac1d626fc909d6fd9f2f4692130949b83e..5abbcfde0db55e1ac0157fbb64ab94a4300e6544 100644 GIT binary patch literal 192 zcmbz@T8!z`$s+fPtX~%7@WVaYh&)MnlB^|A+BmG*Gz@Sh=CJg}OUKU9J diff --git a/src/xenia/cpu/frontend/test/bin/instr_mulld.dis b/src/xenia/cpu/frontend/test/bin/instr_mulld.dis index 0355d09a1..088a68d3a 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_mulld.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_mulld.dis @@ -4,30 +4,78 @@ Disassembly of section .text: 100000: 7c 64 29 d2 mulld r3,r4,r5 100004: 4e 80 00 20 blr -0000000000100008 : - 100008: 7c 64 29 d2 mulld r3,r4,r5 - 10000c: 4e 80 00 20 blr - -0000000000100010 : +0000000000100008 : + 100008: 38 80 00 01 li r4,1 + 10000c: 38 a0 00 00 li r5,0 100010: 7c 64 29 d2 mulld r3,r4,r5 100014: 4e 80 00 20 blr -0000000000100018 : +0000000000100018 : 100018: 7c 64 29 d2 mulld r3,r4,r5 10001c: 4e 80 00 20 blr -0000000000100020 : - 100020: 7c 64 29 d2 mulld r3,r4,r5 - 100024: 4e 80 00 20 blr - -0000000000100028 : +0000000000100020 : + 100020: 38 80 00 01 li r4,1 + 100024: 38 a0 00 01 li r5,1 100028: 7c 64 29 d2 mulld r3,r4,r5 10002c: 4e 80 00 20 blr -0000000000100030 : +0000000000100030 : 100030: 7c 64 29 d2 mulld r3,r4,r5 100034: 4e 80 00 20 blr -0000000000100038 : - 100038: 7c 64 29 d2 mulld r3,r4,r5 - 10003c: 4e 80 00 20 blr +0000000000100038 : + 100038: 38 80 00 01 li r4,1 + 10003c: 38 a0 ff ff li r5,-1 + 100040: 7c 64 29 d2 mulld r3,r4,r5 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c 64 29 d2 mulld r3,r4,r5 + 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 38 80 00 7b li r4,123 + 100054: 38 a0 ff ff li r5,-1 + 100058: 7c 64 29 d2 mulld r3,r4,r5 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 7c 64 29 d2 mulld r3,r4,r5 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 38 80 ff ff li r4,-1 + 10006c: 38 a0 00 01 li r5,1 + 100070: 7c 64 29 d2 mulld r3,r4,r5 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 7c 64 29 d2 mulld r3,r4,r5 + 10007c: 4e 80 00 20 blr + +0000000000100080 : + 100080: 38 80 ff ff li r4,-1 + 100084: 38 a0 00 02 li r5,2 + 100088: 7c 64 29 d2 mulld r3,r4,r5 + 10008c: 4e 80 00 20 blr + +0000000000100090 : + 100090: 7c 64 29 d2 mulld r3,r4,r5 + 100094: 4e 80 00 20 blr + +0000000000100098 : + 100098: 38 80 00 01 li r4,1 + 10009c: 38 a0 ff ff li r5,-1 + 1000a0: 7c 64 29 d2 mulld r3,r4,r5 + 1000a4: 4e 80 00 20 blr + +00000000001000a8 : + 1000a8: 7c 64 29 d2 mulld r3,r4,r5 + 1000ac: 4e 80 00 20 blr + +00000000001000b0 : + 1000b0: 38 80 ff ff li r4,-1 + 1000b4: 38 a0 ff ff li r5,-1 + 1000b8: 7c 64 29 d2 mulld r3,r4,r5 + 1000bc: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_mulld.map b/src/xenia/cpu/frontend/test/bin/instr_mulld.map index 45aac1f83..126954dc0 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_mulld.map +++ b/src/xenia/cpu/frontend/test/bin/instr_mulld.map @@ -1,8 +1,16 @@ 0000000000000000 t test_mulld_1 -0000000000000008 t test_mulld_2 -0000000000000010 t test_mulld_3 -0000000000000018 t test_mulld_4 -0000000000000020 t test_mulld_5 -0000000000000028 t test_mulld_6 -0000000000000030 t test_mulld_7 -0000000000000038 t test_mulld_8 +0000000000000008 t test_mulld_1_constant +0000000000000018 t test_mulld_2 +0000000000000020 t test_mulld_2_constant +0000000000000030 t test_mulld_3 +0000000000000038 t test_mulld_3_constant +0000000000000048 t test_mulld_4 +0000000000000050 t test_mulld_4_constant +0000000000000060 t test_mulld_5 +0000000000000068 t test_mulld_5_constant +0000000000000078 t test_mulld_6 +0000000000000080 t test_mulld_6_constant +0000000000000090 t test_mulld_7 +0000000000000098 t test_mulld_7_constant +00000000000000a8 t test_mulld_8 +00000000000000b0 t test_mulld_8_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_mulli.bin b/src/xenia/cpu/frontend/test/bin/instr_mulli.bin index e9038f7ac9b66672a6e30d8a400e4579813da5f1..c4ecb5c30a7e01948f64c59467622bddb1cf436f 100644 GIT binary patch literal 160 zcmb11VPNoUU{J7VU|^JivVk-sk{FmRlk)#RLJY!2603%>5qkgshp~Y)6GSgq49te9 NhuDj59!MQT3;+q7GZFv* literal 64 gcmb11VPNoUU{H`rVPJ&N|No=XFmVPZRB?zp06*>%Z2$lO diff --git a/src/xenia/cpu/frontend/test/bin/instr_mulli.dis b/src/xenia/cpu/frontend/test/bin/instr_mulli.dis index 105c0b833..edcaa010c 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_mulli.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_mulli.dis @@ -4,30 +4,70 @@ Disassembly of section .text: 100000: 1c 64 00 00 mulli r3,r4,0 100004: 4e 80 00 20 blr -0000000000100008 : - 100008: 1c 64 00 01 mulli r3,r4,1 - 10000c: 4e 80 00 20 blr +0000000000100008 : + 100008: 38 80 00 01 li r4,1 + 10000c: 1c 64 00 00 mulli r3,r4,0 + 100010: 4e 80 00 20 blr -0000000000100010 : - 100010: 1c 64 ff ff mulli r3,r4,-1 - 100014: 4e 80 00 20 blr +0000000000100014 : + 100014: 1c 64 00 01 mulli r3,r4,1 + 100018: 4e 80 00 20 blr -0000000000100018 : - 100018: 1c 64 ff ff mulli r3,r4,-1 - 10001c: 4e 80 00 20 blr - -0000000000100020 : +000000000010001c : + 10001c: 38 80 00 01 li r4,1 100020: 1c 64 00 01 mulli r3,r4,1 100024: 4e 80 00 20 blr -0000000000100028 : - 100028: 1c 64 00 02 mulli r3,r4,2 +0000000000100028 : + 100028: 1c 64 ff ff mulli r3,r4,-1 10002c: 4e 80 00 20 blr -0000000000100030 : - 100030: 1c 64 ff ff mulli r3,r4,-1 - 100034: 4e 80 00 20 blr +0000000000100030 : + 100030: 38 80 00 01 li r4,1 + 100034: 1c 64 ff ff mulli r3,r4,-1 + 100038: 4e 80 00 20 blr -0000000000100038 : - 100038: 1c 64 ff ff mulli r3,r4,-1 - 10003c: 4e 80 00 20 blr +000000000010003c : + 10003c: 1c 64 ff ff mulli r3,r4,-1 + 100040: 4e 80 00 20 blr + +0000000000100044 : + 100044: 38 80 00 7b li r4,123 + 100048: 1c 64 ff ff mulli r3,r4,-1 + 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 1c 64 00 01 mulli r3,r4,1 + 100054: 4e 80 00 20 blr + +0000000000100058 : + 100058: 38 80 ff ff li r4,-1 + 10005c: 1c 64 00 01 mulli r3,r4,1 + 100060: 4e 80 00 20 blr + +0000000000100064 : + 100064: 1c 64 00 02 mulli r3,r4,2 + 100068: 4e 80 00 20 blr + +000000000010006c : + 10006c: 38 80 ff ff li r4,-1 + 100070: 1c 64 00 02 mulli r3,r4,2 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 1c 64 ff ff mulli r3,r4,-1 + 10007c: 4e 80 00 20 blr + +0000000000100080 : + 100080: 38 80 00 01 li r4,1 + 100084: 1c 64 ff ff mulli r3,r4,-1 + 100088: 4e 80 00 20 blr + +000000000010008c : + 10008c: 1c 64 ff ff mulli r3,r4,-1 + 100090: 4e 80 00 20 blr + +0000000000100094 : + 100094: 38 80 ff ff li r4,-1 + 100098: 1c 64 ff ff mulli r3,r4,-1 + 10009c: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_mulli.map b/src/xenia/cpu/frontend/test/bin/instr_mulli.map index e173e7d9d..01ad7cbad 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_mulli.map +++ b/src/xenia/cpu/frontend/test/bin/instr_mulli.map @@ -1,8 +1,16 @@ 0000000000000000 t test_mulli_1 -0000000000000008 t test_mulli_2 -0000000000000010 t test_mulli_3 -0000000000000018 t test_mulli_4 -0000000000000020 t test_mulli_5 -0000000000000028 t test_mulli_6 -0000000000000030 t test_mulli_7 -0000000000000038 t test_mulli_8 +0000000000000008 t test_mulli_1_constant +0000000000000014 t test_mulli_2 +000000000000001c t test_mulli_2_constant +0000000000000028 t test_mulli_3 +0000000000000030 t test_mulli_3_constant +000000000000003c t test_mulli_4 +0000000000000044 t test_mulli_4_constant +0000000000000050 t test_mulli_5 +0000000000000058 t test_mulli_5_constant +0000000000000064 t test_mulli_6 +000000000000006c t test_mulli_6_constant +0000000000000078 t test_mulli_7 +0000000000000080 t test_mulli_7_constant +000000000000008c t test_mulli_8 +0000000000000094 t test_mulli_8_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_mullw.bin b/src/xenia/cpu/frontend/test/bin/instr_mullw.bin index f74ec3f83bb74eb2a5f394f4944ba4e5606c0f69..e519d5aa35d43f8b702a9806127e3f134b952e50 100644 GIT binary patch literal 276 zcmbLG=EG>1JrzqC5@2Ega&%~M literal 88 Scmb: - 100008: 7c 64 29 d6 mullw r3,r4,r5 - 10000c: 4e 80 00 20 blr - -0000000000100010 : +0000000000100008 : + 100008: 38 80 00 01 li r4,1 + 10000c: 38 a0 00 00 li r5,0 100010: 7c 64 29 d6 mullw r3,r4,r5 100014: 4e 80 00 20 blr -0000000000100018 : +0000000000100018 : 100018: 7c 64 29 d6 mullw r3,r4,r5 10001c: 4e 80 00 20 blr -0000000000100020 : - 100020: 7c 64 29 d6 mullw r3,r4,r5 - 100024: 4e 80 00 20 blr - -0000000000100028 : +0000000000100020 : + 100020: 38 80 00 01 li r4,1 + 100024: 38 a0 00 01 li r5,1 100028: 7c 64 29 d6 mullw r3,r4,r5 10002c: 4e 80 00 20 blr -0000000000100030 : +0000000000100030 : 100030: 7c 64 29 d6 mullw r3,r4,r5 100034: 4e 80 00 20 blr -0000000000100038 : - 100038: 7c 64 29 d6 mullw r3,r4,r5 - 10003c: 4e 80 00 20 blr - -0000000000100040 : +0000000000100038 : + 100038: 38 80 00 01 li r4,1 + 10003c: 38 a0 ff ff li r5,-1 100040: 7c 64 29 d6 mullw r3,r4,r5 100044: 4e 80 00 20 blr -0000000000100048 : +0000000000100048 : 100048: 7c 64 29 d6 mullw r3,r4,r5 10004c: 4e 80 00 20 blr -0000000000100050 : - 100050: 7c 64 29 d6 mullw r3,r4,r5 - 100054: 4e 80 00 20 blr +0000000000100050 : + 100050: 38 80 00 7b li r4,123 + 100054: 38 a0 ff ff li r5,-1 + 100058: 7c 64 29 d6 mullw r3,r4,r5 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 7c 64 29 d6 mullw r3,r4,r5 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 38 80 ff ff li r4,-1 + 10006c: 38 a0 00 01 li r5,1 + 100070: 7c 64 29 d6 mullw r3,r4,r5 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 7c 64 29 d6 mullw r3,r4,r5 + 10007c: 4e 80 00 20 blr + +0000000000100080 : + 100080: 38 80 ff ff li r4,-1 + 100084: 38 a0 00 02 li r5,2 + 100088: 7c 64 29 d6 mullw r3,r4,r5 + 10008c: 4e 80 00 20 blr + +0000000000100090 : + 100090: 7c 64 29 d6 mullw r3,r4,r5 + 100094: 4e 80 00 20 blr + +0000000000100098 : + 100098: 38 80 00 01 li r4,1 + 10009c: 38 a0 ff ff li r5,-1 + 1000a0: 7c 64 29 d6 mullw r3,r4,r5 + 1000a4: 4e 80 00 20 blr + +00000000001000a8 : + 1000a8: 7c 64 29 d6 mullw r3,r4,r5 + 1000ac: 4e 80 00 20 blr + +00000000001000b0 : + 1000b0: 38 80 ff ff li r4,-1 + 1000b4: 38 a0 ff ff li r5,-1 + 1000b8: 7c 64 29 d6 mullw r3,r4,r5 + 1000bc: 4e 80 00 20 blr + +00000000001000c0 : + 1000c0: 7c 64 29 d6 mullw r3,r4,r5 + 1000c4: 4e 80 00 20 blr + +00000000001000c8 : + 1000c8: 38 80 ff ff li r4,-1 + 1000cc: 78 84 07 c6 rldicr r4,r4,32,31 + 1000d0: 38 a0 00 01 li r5,1 + 1000d4: 7c 64 29 d6 mullw r3,r4,r5 + 1000d8: 4e 80 00 20 blr + +00000000001000dc : + 1000dc: 7c 64 29 d6 mullw r3,r4,r5 + 1000e0: 4e 80 00 20 blr + +00000000001000e4 : + 1000e4: 38 80 00 01 li r4,1 + 1000e8: 38 a0 ff ff li r5,-1 + 1000ec: 78 a5 07 c6 rldicr r5,r5,32,31 + 1000f0: 7c 64 29 d6 mullw r3,r4,r5 + 1000f4: 4e 80 00 20 blr + +00000000001000f8 : + 1000f8: 7c 64 29 d6 mullw r3,r4,r5 + 1000fc: 4e 80 00 20 blr + +0000000000100100 : + 100100: 38 80 00 01 li r4,1 + 100104: 38 a0 ff ff li r5,-1 + 100108: 78 a5 00 60 clrldi r5,r5,33 + 10010c: 7c 64 29 d6 mullw r3,r4,r5 + 100110: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_mullw.map b/src/xenia/cpu/frontend/test/bin/instr_mullw.map index 6b1f69085..a560eef4b 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_mullw.map +++ b/src/xenia/cpu/frontend/test/bin/instr_mullw.map @@ -1,11 +1,22 @@ 0000000000000000 t test_mullw_1 -0000000000000008 t test_mullw_2 -0000000000000010 t test_mullw_3 -0000000000000018 t test_mullw_4 -0000000000000020 t test_mullw_5 -0000000000000028 t test_mullw_6 -0000000000000030 t test_mullw_7 -0000000000000038 t test_mullw_8 -0000000000000040 t test_mullw_9 -0000000000000048 t test_mullw_10 -0000000000000050 t test_mullw_11 +0000000000000008 t test_mullw_1_constant +0000000000000018 t test_mullw_2 +0000000000000020 t test_mullw_2_constant +0000000000000030 t test_mullw_3 +0000000000000038 t test_mullw_3_constant +0000000000000048 t test_mullw_4 +0000000000000050 t test_mullw_4_constant +0000000000000060 t test_mullw_5 +0000000000000068 t test_mullw_5_constant +0000000000000078 t test_mullw_6 +0000000000000080 t test_mullw_6_constant +0000000000000090 t test_mullw_7 +0000000000000098 t test_mullw_7_constant +00000000000000a8 t test_mullw_8 +00000000000000b0 t test_mullw_8_constant +00000000000000c0 t test_mullw_9 +00000000000000c8 t test_mullw_9_constant +00000000000000dc t test_mullw_10 +00000000000000e4 t test_mullw_10_constant +00000000000000f8 t test_mullw_11 +0000000000000100 t test_mullw_11_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_neg.bin b/src/xenia/cpu/frontend/test/bin/instr_neg.bin index c2031392faf092201f12b7746e41b4a4816cba8a..1724c5460350ba0e3130c4c391dccf2a6bf85312 100644 GIT binary patch literal 68 mcmb: - 100008: 7c 63 00 d0 neg r3,r3 - 10000c: 4e 80 00 20 blr - -0000000000100010 : +0000000000100008 : + 100008: 38 60 00 01 li r3,1 + 10000c: 78 63 f8 24 rldicr r3,r3,31,32 100010: 7c 63 00 d0 neg r3,r3 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c 63 00 d0 neg r3,r3 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 38 60 00 01 li r3,1 + 100024: 78 63 f8 06 rldicr r3,r3,63,0 + 100028: 7c 63 00 d0 neg r3,r3 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 7c 63 00 d0 neg r3,r3 + 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 38 60 00 05 li r3,5 + 10003c: 7c 63 00 d0 neg r3,r3 + 100040: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_neg.map b/src/xenia/cpu/frontend/test/bin/instr_neg.map index b3e4ecf6f..d05eaca56 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_neg.map +++ b/src/xenia/cpu/frontend/test/bin/instr_neg.map @@ -1,3 +1,6 @@ 0000000000000000 t test_neg_1 -0000000000000008 t test_neg_2 -0000000000000010 t test_neg_3 +0000000000000008 t test_neg_1_constant +0000000000000018 t test_neg_2 +0000000000000020 t test_neg_2_constant +0000000000000030 t test_neg_3 +0000000000000038 t test_neg_3_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_nor.bin b/src/xenia/cpu/frontend/test/bin/instr_nor.bin index 4155f59f99e0af259b3d4fa4e0dce96030a83c1c..7499b6c86201c17f7110f477eb3a4743732d9e3f 100644 GIT binary patch delta 15 WcmWeJm>|Mok?{Y2MKXiJ1Q7ryM+GJT delta 4 LcmXpInIHlH0yF^W diff --git a/src/xenia/cpu/frontend/test/bin/instr_nor.dis b/src/xenia/cpu/frontend/test/bin/instr_nor.dis index 5108ff482..cb7685360 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_nor.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_nor.dis @@ -8,3 +8,14 @@ Disassembly of section .text: 0000000000100010 <.nor_cr_1_ne>: 100010: 4e 80 00 20 blr + +0000000000100014 : + 100014: 38 60 ff ff li r3,-1 + 100018: 78 63 00 20 clrldi r3,r3,32 + 10001c: 7c 63 18 f9 not. r3,r3 + 100020: 38 60 00 00 li r3,0 + 100024: 40 82 00 08 bne 10002c <.nor_cr_1_constant_ne> + 100028: 38 60 00 01 li r3,1 + +000000000010002c <.nor_cr_1_constant_ne>: + 10002c: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_nor.map b/src/xenia/cpu/frontend/test/bin/instr_nor.map index 82e154c02..13c7d3d1e 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_nor.map +++ b/src/xenia/cpu/frontend/test/bin/instr_nor.map @@ -1,2 +1,4 @@ 0000000000000000 t test_nor_cr_1 0000000000000010 t .nor_cr_1_ne +0000000000000014 t test_nor_cr_1_constant +000000000000002c t .nor_cr_1_constant_ne diff --git a/src/xenia/cpu/frontend/test/bin/instr_ori.bin b/src/xenia/cpu/frontend/test/bin/instr_ori.bin index 5ddf028d1403ee1ab842d59bb37f83e9273eb570..7c5873993a7927b37fd010006a57761e9e8cff5f 100644 GIT binary patch literal 64 scmYdj{&&Z(fkDBh;ojPWmVNIlTG)>zK*eA*vYbtV07FfSbOlTf00u4|E&u=k literal 16 ScmYdj{&&Z(fk7bwN&^5y!UtCX diff --git a/src/xenia/cpu/frontend/test/bin/instr_ori.dis b/src/xenia/cpu/frontend/test/bin/instr_ori.dis index 80f10e2b9..991338f98 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_ori.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_ori.dis @@ -4,6 +4,22 @@ Disassembly of section .text: 100000: 60 83 fe dc ori r3,r4,65244 100004: 4e 80 00 20 blr -0000000000100008 : - 100008: 60 83 fe dc ori r3,r4,65244 - 10000c: 4e 80 00 20 blr +0000000000100008 : + 100008: 3c 80 de ad lis r4,-8531 + 10000c: 60 84 be ef ori r4,r4,48879 + 100010: 78 84 07 c6 rldicr r4,r4,32,31 + 100014: 60 83 fe dc ori r3,r4,65244 + 100018: 4e 80 00 20 blr + +000000000010001c : + 10001c: 60 83 fe dc ori r3,r4,65244 + 100020: 4e 80 00 20 blr + +0000000000100024 : + 100024: 3c 80 de ad lis r4,-8531 + 100028: 60 84 be ef ori r4,r4,48879 + 10002c: 78 84 07 c6 rldicr r4,r4,32,31 + 100030: 3c 60 10 00 lis r3,4096 + 100034: 7c 84 1b 78 or r4,r4,r3 + 100038: 60 83 fe dc ori r3,r4,65244 + 10003c: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_ori.map b/src/xenia/cpu/frontend/test/bin/instr_ori.map index 63737967f..8b3982507 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_ori.map +++ b/src/xenia/cpu/frontend/test/bin/instr_ori.map @@ -1,2 +1,4 @@ 0000000000000000 t test_ori_1 -0000000000000008 t test_ori_2 +0000000000000008 t test_ori_1_constant +000000000000001c t test_ori_2 +0000000000000024 t test_ori_2_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_rldicl.bin b/src/xenia/cpu/frontend/test/bin/instr_rldicl.bin index 1b8e7abd071e3f65482c5c4cd5e5616d8aa1ce87..1c26ec42a1cd3fcff8b781c3bc0121f9a6868212 100644 GIT binary patch literal 640 zcmbuUY^4a$l$qWiLEz%VgP&F0Jhlo%MQB%=; z`~hKeA!;g`8Hg|!qNbvmod|OwYATwUh%gtTrlR==6Jhs4)KoP8e?(X6%YJ`: - 100008: 78 83 c2 00 rldicl r3,r4,24,8 - 10000c: 4e 80 00 20 blr +0000000000100008 : + 100008: 3c 80 01 23 lis r4,291 + 10000c: 60 84 45 67 ori r4,r4,17767 + 100010: 78 84 07 c6 rldicr r4,r4,32,31 + 100014: 3c 60 89 ab lis r3,-30293 + 100018: 60 63 cd ef ori r3,r3,52719 + 10001c: 78 63 00 20 clrldi r3,r3,32 + 100020: 7c 84 1b 78 or r4,r4,r3 + 100024: 78 83 c0 00 rotldi r3,r4,24 + 100028: 4e 80 00 20 blr -0000000000100010 : - 100010: 78 83 c7 e0 rldicl r3,r4,24,63 - 100014: 4e 80 00 20 blr +000000000010002c : + 10002c: 78 83 c2 00 rldicl r3,r4,24,8 + 100030: 4e 80 00 20 blr -0000000000100018 : - 100018: 78 83 00 00 rotldi r3,r4,0 - 10001c: 4e 80 00 20 blr +0000000000100034 : + 100034: 3c 80 01 23 lis r4,291 + 100038: 60 84 45 67 ori r4,r4,17767 + 10003c: 78 84 07 c6 rldicr r4,r4,32,31 + 100040: 3c 60 89 ab lis r3,-30293 + 100044: 60 63 cd ef ori r3,r3,52719 + 100048: 78 63 00 20 clrldi r3,r3,32 + 10004c: 7c 84 1b 78 or r4,r4,r3 + 100050: 78 83 c2 00 rldicl r3,r4,24,8 + 100054: 4e 80 00 20 blr -0000000000100020 : - 100020: 78 83 07 e0 clrldi r3,r4,63 - 100024: 4e 80 00 20 blr +0000000000100058 : + 100058: 78 83 c7 e0 rldicl r3,r4,24,63 + 10005c: 4e 80 00 20 blr -0000000000100028 : - 100028: 78 83 02 00 clrldi r3,r4,8 - 10002c: 4e 80 00 20 blr +0000000000100060 : + 100060: 3c 80 01 23 lis r4,291 + 100064: 60 84 45 67 ori r4,r4,17767 + 100068: 78 84 07 c6 rldicr r4,r4,32,31 + 10006c: 3c 60 89 ab lis r3,-30293 + 100070: 60 63 cd ef ori r3,r3,52719 + 100074: 78 63 00 20 clrldi r3,r3,32 + 100078: 7c 84 1b 78 or r4,r4,r3 + 10007c: 78 83 c7 e0 rldicl r3,r4,24,63 + 100080: 4e 80 00 20 blr -0000000000100030 : - 100030: 78 83 f8 02 rotldi r3,r4,63 - 100034: 4e 80 00 20 blr +0000000000100084 : + 100084: 78 83 00 00 rotldi r3,r4,0 + 100088: 4e 80 00 20 blr -0000000000100038 : - 100038: 78 83 ff e2 rldicl r3,r4,63,63 - 10003c: 4e 80 00 20 blr +000000000010008c : + 10008c: 3c 80 01 23 lis r4,291 + 100090: 60 84 45 67 ori r4,r4,17767 + 100094: 78 84 07 c6 rldicr r4,r4,32,31 + 100098: 3c 60 89 ab lis r3,-30293 + 10009c: 60 63 cd ef ori r3,r3,52719 + 1000a0: 78 63 00 20 clrldi r3,r3,32 + 1000a4: 7c 84 1b 78 or r4,r4,r3 + 1000a8: 78 83 00 00 rotldi r3,r4,0 + 1000ac: 4e 80 00 20 blr -0000000000100040 : - 100040: 78 83 f8 00 rotldi r3,r4,31 - 100044: 4e 80 00 20 blr +00000000001000b0 : + 1000b0: 78 83 07 e0 clrldi r3,r4,63 + 1000b4: 4e 80 00 20 blr -0000000000100048 : - 100048: 78 83 d1 82 rldicl r3,r4,58,6 - 10004c: 4e 80 00 20 blr +00000000001000b8 : + 1000b8: 3c 80 01 23 lis r4,291 + 1000bc: 60 84 45 67 ori r4,r4,17767 + 1000c0: 78 84 07 c6 rldicr r4,r4,32,31 + 1000c4: 3c 60 89 ab lis r3,-30293 + 1000c8: 60 63 cd ef ori r3,r3,52719 + 1000cc: 78 63 00 20 clrldi r3,r3,32 + 1000d0: 7c 84 1b 78 or r4,r4,r3 + 1000d4: 78 83 07 e0 clrldi r3,r4,63 + 1000d8: 4e 80 00 20 blr -0000000000100050 : - 100050: 78 63 00 00 rotldi r3,r3,0 - 100054: 78 84 00 00 rotldi r4,r4,0 - 100058: 4e 80 00 20 blr +00000000001000dc : + 1000dc: 78 83 02 00 clrldi r3,r4,8 + 1000e0: 4e 80 00 20 blr -000000000010005c : - 10005c: 78 63 f8 42 rldicl r3,r3,63,1 - 100060: 78 84 f8 42 rldicl r4,r4,63,1 - 100064: 4e 80 00 20 blr +00000000001000e4 : + 1000e4: 3c 80 01 23 lis r4,291 + 1000e8: 60 84 45 67 ori r4,r4,17767 + 1000ec: 78 84 07 c6 rldicr r4,r4,32,31 + 1000f0: 3c 60 89 ab lis r3,-30293 + 1000f4: 60 63 cd ef ori r3,r3,52719 + 1000f8: 78 63 00 20 clrldi r3,r3,32 + 1000fc: 7c 84 1b 78 or r4,r4,r3 + 100100: 78 83 02 00 clrldi r3,r4,8 + 100104: 4e 80 00 20 blr -0000000000100068 : - 100068: 78 63 00 22 rldicl r3,r3,32,32 - 10006c: 78 84 00 22 rldicl r4,r4,32,32 - 100070: 4e 80 00 20 blr +0000000000100108 : + 100108: 78 83 f8 02 rotldi r3,r4,63 + 10010c: 4e 80 00 20 blr -0000000000100074 : - 100074: 78 63 0f e0 rldicl r3,r3,1,63 - 100078: 78 84 0f e0 rldicl r4,r4,1,63 - 10007c: 4e 80 00 20 blr +0000000000100110 : + 100110: 3c 80 01 23 lis r4,291 + 100114: 60 84 45 67 ori r4,r4,17767 + 100118: 78 84 07 c6 rldicr r4,r4,32,31 + 10011c: 3c 60 89 ab lis r3,-30293 + 100120: 60 63 cd ef ori r3,r3,52719 + 100124: 78 63 00 20 clrldi r3,r3,32 + 100128: 7c 84 1b 78 or r4,r4,r3 + 10012c: 78 83 f8 02 rotldi r3,r4,63 + 100130: 4e 80 00 20 blr + +0000000000100134 : + 100134: 78 83 ff e2 rldicl r3,r4,63,63 + 100138: 4e 80 00 20 blr + +000000000010013c : + 10013c: 3c 80 01 23 lis r4,291 + 100140: 60 84 45 67 ori r4,r4,17767 + 100144: 78 84 07 c6 rldicr r4,r4,32,31 + 100148: 3c 60 89 ab lis r3,-30293 + 10014c: 60 63 cd ef ori r3,r3,52719 + 100150: 78 63 00 20 clrldi r3,r3,32 + 100154: 7c 84 1b 78 or r4,r4,r3 + 100158: 78 83 ff e2 rldicl r3,r4,63,63 + 10015c: 4e 80 00 20 blr + +0000000000100160 : + 100160: 78 83 f8 00 rotldi r3,r4,31 + 100164: 4e 80 00 20 blr + +0000000000100168 : + 100168: 3c 80 01 23 lis r4,291 + 10016c: 60 84 45 67 ori r4,r4,17767 + 100170: 78 84 07 c6 rldicr r4,r4,32,31 + 100174: 3c 60 89 ab lis r3,-30293 + 100178: 60 63 cd ef ori r3,r3,52719 + 10017c: 78 63 00 20 clrldi r3,r3,32 + 100180: 7c 84 1b 78 or r4,r4,r3 + 100184: 78 83 f8 00 rotldi r3,r4,31 + 100188: 4e 80 00 20 blr + +000000000010018c : + 10018c: 78 83 d1 82 rldicl r3,r4,58,6 + 100190: 4e 80 00 20 blr + +0000000000100194 : + 100194: 3c 80 16 30 lis r4,5680 + 100198: 78 83 d1 82 rldicl r3,r4,58,6 + 10019c: 4e 80 00 20 blr + +00000000001001a0 : + 1001a0: 78 63 00 00 rotldi r3,r3,0 + 1001a4: 78 84 00 00 rotldi r4,r4,0 + 1001a8: 4e 80 00 20 blr + +00000000001001ac : + 1001ac: 3c 80 01 23 lis r4,291 + 1001b0: 60 84 45 67 ori r4,r4,17767 + 1001b4: 78 84 07 c6 rldicr r4,r4,32,31 + 1001b8: 3c 60 89 ab lis r3,-30293 + 1001bc: 60 63 cd ef ori r3,r3,52719 + 1001c0: 78 63 00 20 clrldi r3,r3,32 + 1001c4: 7c 84 1b 78 or r4,r4,r3 + 1001c8: 38 60 ff ff li r3,-1 + 1001cc: 78 63 00 00 rotldi r3,r3,0 + 1001d0: 78 84 00 00 rotldi r4,r4,0 + 1001d4: 4e 80 00 20 blr + +00000000001001d8 : + 1001d8: 78 63 f8 42 rldicl r3,r3,63,1 + 1001dc: 78 84 f8 42 rldicl r4,r4,63,1 + 1001e0: 4e 80 00 20 blr + +00000000001001e4 : + 1001e4: 3c 80 01 23 lis r4,291 + 1001e8: 60 84 45 67 ori r4,r4,17767 + 1001ec: 78 84 07 c6 rldicr r4,r4,32,31 + 1001f0: 3c 60 89 ab lis r3,-30293 + 1001f4: 60 63 cd ef ori r3,r3,52719 + 1001f8: 78 63 00 20 clrldi r3,r3,32 + 1001fc: 7c 84 1b 78 or r4,r4,r3 + 100200: 38 60 ff ff li r3,-1 + 100204: 78 63 f8 42 rldicl r3,r3,63,1 + 100208: 78 84 f8 42 rldicl r4,r4,63,1 + 10020c: 4e 80 00 20 blr + +0000000000100210 : + 100210: 78 63 00 22 rldicl r3,r3,32,32 + 100214: 78 84 00 22 rldicl r4,r4,32,32 + 100218: 4e 80 00 20 blr + +000000000010021c : + 10021c: 3c 80 01 23 lis r4,291 + 100220: 60 84 45 67 ori r4,r4,17767 + 100224: 78 84 07 c6 rldicr r4,r4,32,31 + 100228: 3c 60 89 ab lis r3,-30293 + 10022c: 60 63 cd ef ori r3,r3,52719 + 100230: 78 63 00 20 clrldi r3,r3,32 + 100234: 7c 84 1b 78 or r4,r4,r3 + 100238: 38 60 ff ff li r3,-1 + 10023c: 78 63 00 22 rldicl r3,r3,32,32 + 100240: 78 84 00 22 rldicl r4,r4,32,32 + 100244: 4e 80 00 20 blr + +0000000000100248 : + 100248: 78 63 0f e0 rldicl r3,r3,1,63 + 10024c: 78 84 0f e0 rldicl r4,r4,1,63 + 100250: 4e 80 00 20 blr + +0000000000100254 : + 100254: 3c 80 01 23 lis r4,291 + 100258: 60 84 45 67 ori r4,r4,17767 + 10025c: 78 84 07 c6 rldicr r4,r4,32,31 + 100260: 3c 60 89 ab lis r3,-30293 + 100264: 60 63 cd ef ori r3,r3,52719 + 100268: 78 63 00 20 clrldi r3,r3,32 + 10026c: 7c 84 1b 78 or r4,r4,r3 + 100270: 38 60 ff ff li r3,-1 + 100274: 78 63 0f e0 rldicl r3,r3,1,63 + 100278: 78 84 0f e0 rldicl r4,r4,1,63 + 10027c: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_rldicl.map b/src/xenia/cpu/frontend/test/bin/instr_rldicl.map index 2c701aa7b..188925358 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_rldicl.map +++ b/src/xenia/cpu/frontend/test/bin/instr_rldicl.map @@ -1,14 +1,28 @@ 0000000000000000 t test_rldicl_1 -0000000000000008 t test_rldicl_2 -0000000000000010 t test_rldicl_3 -0000000000000018 t test_rldicl_4 -0000000000000020 t test_rldicl_5 -0000000000000028 t test_rldicl_6 -0000000000000030 t test_rldicl_7 -0000000000000038 t test_rldicl_8 -0000000000000040 t test_rldicl_9 -0000000000000048 t test_rldicl_10 -0000000000000050 t test_srdi_1 -000000000000005c t test_srdi_2 -0000000000000068 t test_srdi_3 -0000000000000074 t test_srdi_4 +0000000000000008 t test_rldicl_1_constant +000000000000002c t test_rldicl_2 +0000000000000034 t test_rldicl_2_constant +0000000000000058 t test_rldicl_3 +0000000000000060 t test_rldicl_3_constant +0000000000000084 t test_rldicl_4 +000000000000008c t test_rldicl_4_constant +00000000000000b0 t test_rldicl_5 +00000000000000b8 t test_rldicl_5_constant +00000000000000dc t test_rldicl_6 +00000000000000e4 t test_rldicl_6_constant +0000000000000108 t test_rldicl_7 +0000000000000110 t test_rldicl_7_constant +0000000000000134 t test_rldicl_8 +000000000000013c t test_rldicl_8_constant +0000000000000160 t test_rldicl_9 +0000000000000168 t test_rldicl_9_constant +000000000000018c t test_rldicl_10 +0000000000000194 t test_rldicl_10_constant +00000000000001a0 t test_srdi_1 +00000000000001ac t test_srdi_1_constant +00000000000001d8 t test_srdi_2 +00000000000001e4 t test_srdi_2_constant +0000000000000210 t test_srdi_3 +000000000000021c t test_srdi_3_constant +0000000000000248 t test_srdi_4 +0000000000000254 t test_srdi_4_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_rldicr.bin b/src/xenia/cpu/frontend/test/bin/instr_rldicr.bin index 0a6e90dc068716b372acfa04963f8544c82184f2..ee6d7875c9d108b7ada5aeebc9acd68c28585ac2 100644 GIT binary patch literal 620 zcmbuUY^4a$l$qWiLEz%VgP&F0Jhlo%MQB%=; z{0U)mA!;g`8Hg|!qNbvmod|OwYATwUh%gtTrlR==8)5fC)KoP8e@0j>L=DhfBHRE` zQ<2R61Q`AV{b!Nz|39+Yie&yJ6)pTr2)PNO51|%l#xYQQ6Q>WMwj%ilTSW`u@PgQf GPzwN3An>;U literal 120 zcmb6%YJ`? diff --git a/src/xenia/cpu/frontend/test/bin/instr_rldicr.dis b/src/xenia/cpu/frontend/test/bin/instr_rldicr.dis index f0f717f6d..d9aa3d5d8 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_rldicr.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_rldicr.dis @@ -4,54 +4,205 @@ Disassembly of section .text: 100000: 78 83 c0 04 rldicr r3,r4,24,0 100004: 4e 80 00 20 blr -0000000000100008 : - 100008: 78 83 c2 04 rldicr r3,r4,24,8 - 10000c: 4e 80 00 20 blr +0000000000100008 : + 100008: 3c 80 01 23 lis r4,291 + 10000c: 60 84 45 67 ori r4,r4,17767 + 100010: 78 84 07 c6 rldicr r4,r4,32,31 + 100014: 3c 60 89 ab lis r3,-30293 + 100018: 60 63 cd ef ori r3,r3,52719 + 10001c: 78 63 00 20 clrldi r3,r3,32 + 100020: 7c 84 1b 78 or r4,r4,r3 + 100024: 78 83 c0 04 rldicr r3,r4,24,0 + 100028: 4e 80 00 20 blr -0000000000100010 : - 100010: 78 83 c7 e4 rldicr r3,r4,24,63 - 100014: 4e 80 00 20 blr +000000000010002c : + 10002c: 78 83 c2 04 rldicr r3,r4,24,8 + 100030: 4e 80 00 20 blr -0000000000100018 : - 100018: 78 83 00 04 rldicr r3,r4,0,0 - 10001c: 4e 80 00 20 blr +0000000000100034 : + 100034: 3c 80 01 23 lis r4,291 + 100038: 60 84 45 67 ori r4,r4,17767 + 10003c: 78 84 07 c6 rldicr r4,r4,32,31 + 100040: 3c 60 89 ab lis r3,-30293 + 100044: 60 63 cd ef ori r3,r3,52719 + 100048: 78 63 00 20 clrldi r3,r3,32 + 10004c: 7c 84 1b 78 or r4,r4,r3 + 100050: 78 83 c2 04 rldicr r3,r4,24,8 + 100054: 4e 80 00 20 blr -0000000000100020 : - 100020: 78 83 07 e4 rldicr r3,r4,0,63 - 100024: 4e 80 00 20 blr - -0000000000100028 : - 100028: 78 83 02 04 rldicr r3,r4,0,8 - 10002c: 4e 80 00 20 blr - -0000000000100030 : - 100030: 78 83 f8 06 rldicr r3,r4,63,0 - 100034: 4e 80 00 20 blr - -0000000000100038 : - 100038: 78 83 ff e6 rldicr r3,r4,63,63 - 10003c: 4e 80 00 20 blr - -0000000000100040 : - 100040: 78 83 f8 04 rldicr r3,r4,31,0 - 100044: 4e 80 00 20 blr - -0000000000100048 : - 100048: 78 63 07 e4 rldicr r3,r3,0,63 - 10004c: 78 84 07 e4 rldicr r4,r4,0,63 - 100050: 4e 80 00 20 blr - -0000000000100054 : - 100054: 78 63 0f a4 rldicr r3,r3,1,62 - 100058: 78 84 0f a4 rldicr r4,r4,1,62 +0000000000100058 : + 100058: 78 83 c7 e4 rldicr r3,r4,24,63 10005c: 4e 80 00 20 blr -0000000000100060 : - 100060: 78 63 07 c6 rldicr r3,r3,32,31 - 100064: 78 84 07 c6 rldicr r4,r4,32,31 - 100068: 4e 80 00 20 blr +0000000000100060 : + 100060: 3c 80 01 23 lis r4,291 + 100064: 60 84 45 67 ori r4,r4,17767 + 100068: 78 84 07 c6 rldicr r4,r4,32,31 + 10006c: 3c 60 89 ab lis r3,-30293 + 100070: 60 63 cd ef ori r3,r3,52719 + 100074: 78 63 00 20 clrldi r3,r3,32 + 100078: 7c 84 1b 78 or r4,r4,r3 + 10007c: 78 83 c7 e4 rldicr r3,r4,24,63 + 100080: 4e 80 00 20 blr -000000000010006c : - 10006c: 78 63 f8 06 rldicr r3,r3,63,0 - 100070: 78 84 f8 06 rldicr r4,r4,63,0 - 100074: 4e 80 00 20 blr +0000000000100084 : + 100084: 78 83 00 04 rldicr r3,r4,0,0 + 100088: 4e 80 00 20 blr + +000000000010008c : + 10008c: 3c 80 01 23 lis r4,291 + 100090: 60 84 45 67 ori r4,r4,17767 + 100094: 78 84 07 c6 rldicr r4,r4,32,31 + 100098: 3c 60 89 ab lis r3,-30293 + 10009c: 60 63 cd ef ori r3,r3,52719 + 1000a0: 78 63 00 20 clrldi r3,r3,32 + 1000a4: 7c 84 1b 78 or r4,r4,r3 + 1000a8: 78 83 00 04 rldicr r3,r4,0,0 + 1000ac: 4e 80 00 20 blr + +00000000001000b0 : + 1000b0: 78 83 07 e4 rldicr r3,r4,0,63 + 1000b4: 4e 80 00 20 blr + +00000000001000b8 : + 1000b8: 3c 80 01 23 lis r4,291 + 1000bc: 60 84 45 67 ori r4,r4,17767 + 1000c0: 78 84 07 c6 rldicr r4,r4,32,31 + 1000c4: 3c 60 89 ab lis r3,-30293 + 1000c8: 60 63 cd ef ori r3,r3,52719 + 1000cc: 78 63 00 20 clrldi r3,r3,32 + 1000d0: 7c 84 1b 78 or r4,r4,r3 + 1000d4: 78 83 07 e4 rldicr r3,r4,0,63 + 1000d8: 4e 80 00 20 blr + +00000000001000dc : + 1000dc: 78 83 02 04 rldicr r3,r4,0,8 + 1000e0: 4e 80 00 20 blr + +00000000001000e4 : + 1000e4: 3c 80 01 23 lis r4,291 + 1000e8: 60 84 45 67 ori r4,r4,17767 + 1000ec: 78 84 07 c6 rldicr r4,r4,32,31 + 1000f0: 3c 60 89 ab lis r3,-30293 + 1000f4: 60 63 cd ef ori r3,r3,52719 + 1000f8: 78 63 00 20 clrldi r3,r3,32 + 1000fc: 7c 84 1b 78 or r4,r4,r3 + 100100: 78 83 02 04 rldicr r3,r4,0,8 + 100104: 4e 80 00 20 blr + +0000000000100108 : + 100108: 78 83 f8 06 rldicr r3,r4,63,0 + 10010c: 4e 80 00 20 blr + +0000000000100110 : + 100110: 3c 80 01 23 lis r4,291 + 100114: 60 84 45 67 ori r4,r4,17767 + 100118: 78 84 07 c6 rldicr r4,r4,32,31 + 10011c: 3c 60 89 ab lis r3,-30293 + 100120: 60 63 cd ef ori r3,r3,52719 + 100124: 78 63 00 20 clrldi r3,r3,32 + 100128: 7c 84 1b 78 or r4,r4,r3 + 10012c: 78 83 f8 06 rldicr r3,r4,63,0 + 100130: 4e 80 00 20 blr + +0000000000100134 : + 100134: 78 83 ff e6 rldicr r3,r4,63,63 + 100138: 4e 80 00 20 blr + +000000000010013c : + 10013c: 3c 80 01 23 lis r4,291 + 100140: 60 84 45 67 ori r4,r4,17767 + 100144: 78 84 07 c6 rldicr r4,r4,32,31 + 100148: 3c 60 89 ab lis r3,-30293 + 10014c: 60 63 cd ef ori r3,r3,52719 + 100150: 78 63 00 20 clrldi r3,r3,32 + 100154: 7c 84 1b 78 or r4,r4,r3 + 100158: 78 83 ff e6 rldicr r3,r4,63,63 + 10015c: 4e 80 00 20 blr + +0000000000100160 : + 100160: 78 83 f8 04 rldicr r3,r4,31,0 + 100164: 4e 80 00 20 blr + +0000000000100168 : + 100168: 3c 80 01 23 lis r4,291 + 10016c: 60 84 45 67 ori r4,r4,17767 + 100170: 78 84 07 c6 rldicr r4,r4,32,31 + 100174: 3c 60 89 ab lis r3,-30293 + 100178: 60 63 cd ef ori r3,r3,52719 + 10017c: 78 63 00 20 clrldi r3,r3,32 + 100180: 7c 84 1b 78 or r4,r4,r3 + 100184: 78 83 f8 04 rldicr r3,r4,31,0 + 100188: 4e 80 00 20 blr + +000000000010018c : + 10018c: 78 63 07 e4 rldicr r3,r3,0,63 + 100190: 78 84 07 e4 rldicr r4,r4,0,63 + 100194: 4e 80 00 20 blr + +0000000000100198 : + 100198: 3c 80 01 23 lis r4,291 + 10019c: 60 84 45 67 ori r4,r4,17767 + 1001a0: 78 84 07 c6 rldicr r4,r4,32,31 + 1001a4: 3c 60 89 ab lis r3,-30293 + 1001a8: 60 63 cd ef ori r3,r3,52719 + 1001ac: 78 63 00 20 clrldi r3,r3,32 + 1001b0: 7c 84 1b 78 or r4,r4,r3 + 1001b4: 38 60 ff ff li r3,-1 + 1001b8: 78 63 07 e4 rldicr r3,r3,0,63 + 1001bc: 78 84 07 e4 rldicr r4,r4,0,63 + 1001c0: 4e 80 00 20 blr + +00000000001001c4 : + 1001c4: 78 63 0f a4 rldicr r3,r3,1,62 + 1001c8: 78 84 0f a4 rldicr r4,r4,1,62 + 1001cc: 4e 80 00 20 blr + +00000000001001d0 : + 1001d0: 3c 80 01 23 lis r4,291 + 1001d4: 60 84 45 67 ori r4,r4,17767 + 1001d8: 78 84 07 c6 rldicr r4,r4,32,31 + 1001dc: 3c 60 89 ab lis r3,-30293 + 1001e0: 60 63 cd ef ori r3,r3,52719 + 1001e4: 78 63 00 20 clrldi r3,r3,32 + 1001e8: 7c 84 1b 78 or r4,r4,r3 + 1001ec: 38 60 ff ff li r3,-1 + 1001f0: 78 63 0f a4 rldicr r3,r3,1,62 + 1001f4: 78 84 0f a4 rldicr r4,r4,1,62 + 1001f8: 4e 80 00 20 blr + +00000000001001fc : + 1001fc: 78 63 07 c6 rldicr r3,r3,32,31 + 100200: 78 84 07 c6 rldicr r4,r4,32,31 + 100204: 4e 80 00 20 blr + +0000000000100208 : + 100208: 3c 80 01 23 lis r4,291 + 10020c: 60 84 45 67 ori r4,r4,17767 + 100210: 78 84 07 c6 rldicr r4,r4,32,31 + 100214: 3c 60 89 ab lis r3,-30293 + 100218: 60 63 cd ef ori r3,r3,52719 + 10021c: 78 63 00 20 clrldi r3,r3,32 + 100220: 7c 84 1b 78 or r4,r4,r3 + 100224: 38 60 ff ff li r3,-1 + 100228: 78 63 07 c6 rldicr r3,r3,32,31 + 10022c: 78 84 07 c6 rldicr r4,r4,32,31 + 100230: 4e 80 00 20 blr + +0000000000100234 : + 100234: 78 63 f8 06 rldicr r3,r3,63,0 + 100238: 78 84 f8 06 rldicr r4,r4,63,0 + 10023c: 4e 80 00 20 blr + +0000000000100240 : + 100240: 3c 80 01 23 lis r4,291 + 100244: 60 84 45 67 ori r4,r4,17767 + 100248: 78 84 07 c6 rldicr r4,r4,32,31 + 10024c: 3c 60 89 ab lis r3,-30293 + 100250: 60 63 cd ef ori r3,r3,52719 + 100254: 78 63 00 20 clrldi r3,r3,32 + 100258: 7c 84 1b 78 or r4,r4,r3 + 10025c: 38 60 ff ff li r3,-1 + 100260: 78 63 f8 06 rldicr r3,r3,63,0 + 100264: 78 84 f8 06 rldicr r4,r4,63,0 + 100268: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_rldicr.map b/src/xenia/cpu/frontend/test/bin/instr_rldicr.map index b576758fe..de7bbecb2 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_rldicr.map +++ b/src/xenia/cpu/frontend/test/bin/instr_rldicr.map @@ -1,13 +1,26 @@ 0000000000000000 t test_rldicr_1 -0000000000000008 t test_rldicr_2 -0000000000000010 t test_rldicr_3 -0000000000000018 t test_rldicr_4 -0000000000000020 t test_rldicr_5 -0000000000000028 t test_rldicr_6 -0000000000000030 t test_rldicr_7 -0000000000000038 t test_rldicr_8 -0000000000000040 t test_rldicr_9 -0000000000000048 t test_sldi_1 -0000000000000054 t test_sldi_2 -0000000000000060 t test_sldi_3 -000000000000006c t test_sldi_4 +0000000000000008 t test_rldicr_1_constant +000000000000002c t test_rldicr_2 +0000000000000034 t test_rldicr_2_constant +0000000000000058 t test_rldicr_3 +0000000000000060 t test_rldicr_3_constant +0000000000000084 t test_rldicr_4 +000000000000008c t test_rldicr_4_constant +00000000000000b0 t test_rldicr_5 +00000000000000b8 t test_rldicr_5_constant +00000000000000dc t test_rldicr_6 +00000000000000e4 t test_rldicr_6_constant +0000000000000108 t test_rldicr_7 +0000000000000110 t test_rldicr_7_constant +0000000000000134 t test_rldicr_8 +000000000000013c t test_rldicr_8_constant +0000000000000160 t test_rldicr_9 +0000000000000168 t test_rldicr_9_constant +000000000000018c t test_sldi_1 +0000000000000198 t test_sldi_1_constant +00000000000001c4 t test_sldi_2 +00000000000001d0 t test_sldi_2_constant +00000000000001fc t test_sldi_3 +0000000000000208 t test_sldi_3_constant +0000000000000234 t test_sldi_4 +0000000000000240 t test_sldi_4_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_rlwimi.bin b/src/xenia/cpu/frontend/test/bin/instr_rlwimi.bin index e83c8e941674d4b02f0a8e229ec17ecd4125dfb8..944050d6c336f01d4953cc985f41b6c7f0042878 100644 GIT binary patch literal 72 zcmWG&6R`4YU{J7WIQ1`~W!Jun7WQK{2@@C+k_{Ltk{J|gTBIv%4%}OtaBScEien%- R2A~`RGg$7JbVUGEKL8Mo8wvmb literal 8 PcmWG&6R`4YU{C-63XB2| diff --git a/src/xenia/cpu/frontend/test/bin/instr_rlwimi.dis b/src/xenia/cpu/frontend/test/bin/instr_rlwimi.dis index ecf62b895..1a8414f80 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_rlwimi.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_rlwimi.dis @@ -3,3 +3,21 @@ Disassembly of section .text: 0000000000100000 : 100000: 50 86 10 3a rlwimi r6,r4,2,0,29 100004: 4e 80 00 20 blr + +0000000000100008 : + 100008: 3c 80 ca fe lis r4,-13570 + 10000c: 60 84 ba be ori r4,r4,47806 + 100010: 78 84 07 c6 rldicr r4,r4,32,31 + 100014: 3c 60 90 00 lis r3,-28672 + 100018: 60 63 30 00 ori r3,r3,12288 + 10001c: 78 63 00 20 clrldi r3,r3,32 + 100020: 7c 84 1b 78 or r4,r4,r3 + 100024: 3c c0 de ad lis r6,-8531 + 100028: 60 c6 be ef ori r6,r6,48879 + 10002c: 78 c6 07 c6 rldicr r6,r6,32,31 + 100030: 3c 60 00 00 lis r3,0 + 100034: 60 63 00 03 ori r3,r3,3 + 100038: 78 63 00 20 clrldi r3,r3,32 + 10003c: 7c c6 1b 78 or r6,r6,r3 + 100040: 50 86 10 3a rlwimi r6,r4,2,0,29 + 100044: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_rlwimi.map b/src/xenia/cpu/frontend/test/bin/instr_rlwimi.map index 91f58a94f..83309702c 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_rlwimi.map +++ b/src/xenia/cpu/frontend/test/bin/instr_rlwimi.map @@ -1 +1,2 @@ 0000000000000000 t test_rlwimi +0000000000000008 t test_rlwimi_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_rlwinm.bin b/src/xenia/cpu/frontend/test/bin/instr_rlwinm.bin index f38529b42bd8e032b9ae131adcfaae073703a70a..edc8b1ec93f0cae86ca23c90e73abe99e32a661d 100644 GIT binary patch literal 244 zcmWGp{@%{7fkDAy0fRvZlpWH1NDd@s(;#G$&=OVw#RuJ(C3<)g; z3>7U53NSGsZ4Hszz=9+P77J-+tU@&p!VhU?0J{lcKZFkyS3p${;fFM{ps9!OLz-LA H#36hDf73{3 literal 80 ucmWGp{@%{7fk7dp`H&ohRxpFm0#;Dk8bUKxL1+f3dIkjup9RWq0n-4`78a}k diff --git a/src/xenia/cpu/frontend/test/bin/instr_rlwinm.dis b/src/xenia/cpu/frontend/test/bin/instr_rlwinm.dis index f16b538d3..061f63561 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_rlwinm.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_rlwinm.dis @@ -4,38 +4,99 @@ Disassembly of section .text: 100000: 54 a7 ef 3e rlwinm r7,r5,29,28,31 100004: 4e 80 00 20 blr -0000000000100008 : - 100008: 54 83 c2 1e rlwinm r3,r4,24,8,15 - 10000c: 4e 80 00 20 blr +0000000000100008 : + 100008: 38 a0 00 30 li r5,48 + 10000c: 54 a7 ef 3e rlwinm r7,r5,29,28,31 + 100010: 4e 80 00 20 blr -0000000000100010 : - 100010: 54 83 20 36 rlwinm r3,r4,4,0,27 - 100014: 4e 80 00 20 blr +0000000000100014 : + 100014: 54 83 c2 1e rlwinm r3,r4,24,8,15 + 100018: 4e 80 00 20 blr -0000000000100018 : - 100018: 54 83 10 3a rlwinm r3,r4,2,0,29 - 10001c: 4e 80 00 20 blr +000000000010001c : + 10001c: 3c 80 12 34 lis r4,4660 + 100020: 60 84 56 78 ori r4,r4,22136 + 100024: 54 83 c2 1e rlwinm r3,r4,24,8,15 + 100028: 4e 80 00 20 blr -0000000000100020 : - 100020: 54 83 10 3b rlwinm. r3,r4,2,0,29 - 100024: 4e 80 00 20 blr +000000000010002c : + 10002c: 54 83 20 36 rlwinm r3,r4,4,0,27 + 100030: 4e 80 00 20 blr -0000000000100028 : - 100028: 54 83 01 7a rlwinm r3,r4,0,5,29 - 10002c: 4e 80 00 20 blr +0000000000100034 : + 100034: 3c 80 12 34 lis r4,4660 + 100038: 60 84 56 78 ori r4,r4,22136 + 10003c: 54 83 20 36 rlwinm r3,r4,4,0,27 + 100040: 4e 80 00 20 blr -0000000000100030 : - 100030: 54 83 00 3e rotlwi r3,r4,0 - 100034: 4e 80 00 20 blr +0000000000100044 : + 100044: 54 83 10 3a rlwinm r3,r4,2,0,29 + 100048: 4e 80 00 20 blr -0000000000100038 : - 100038: 54 83 00 20 rlwinm r3,r4,0,0,16 - 10003c: 4e 80 00 20 blr +000000000010004c : + 10004c: 3c 80 90 00 lis r4,-28672 + 100050: 60 84 30 00 ori r4,r4,12288 + 100054: 78 84 00 20 clrldi r4,r4,32 + 100058: 54 83 10 3a rlwinm r3,r4,2,0,29 + 10005c: 4e 80 00 20 blr -0000000000100040 : - 100040: 54 83 04 3e clrlwi r3,r4,16 - 100044: 4e 80 00 20 blr +0000000000100060 : + 100060: 54 83 10 3b rlwinm. r3,r4,2,0,29 + 100064: 4e 80 00 20 blr -0000000000100048 : - 100048: 54 83 84 3e rlwinm r3,r4,16,16,31 - 10004c: 4e 80 00 20 blr +0000000000100068 : + 100068: 3c 80 b0 04 lis r4,-20476 + 10006c: 60 84 30 00 ori r4,r4,12288 + 100070: 78 84 00 20 clrldi r4,r4,32 + 100074: 54 83 10 3b rlwinm. r3,r4,2,0,29 + 100078: 4e 80 00 20 blr + +000000000010007c : + 10007c: 54 83 01 7a rlwinm r3,r4,0,5,29 + 100080: 4e 80 00 20 blr + +0000000000100084 : + 100084: 3c 80 12 34 lis r4,4660 + 100088: 60 84 56 78 ori r4,r4,22136 + 10008c: 54 83 01 7a rlwinm r3,r4,0,5,29 + 100090: 4e 80 00 20 blr + +0000000000100094 : + 100094: 54 83 00 3e rotlwi r3,r4,0 + 100098: 4e 80 00 20 blr + +000000000010009c : + 10009c: 3c 80 12 34 lis r4,4660 + 1000a0: 60 84 56 78 ori r4,r4,22136 + 1000a4: 54 83 00 3e rotlwi r3,r4,0 + 1000a8: 4e 80 00 20 blr + +00000000001000ac : + 1000ac: 54 83 00 20 rlwinm r3,r4,0,0,16 + 1000b0: 4e 80 00 20 blr + +00000000001000b4 : + 1000b4: 3c 80 12 34 lis r4,4660 + 1000b8: 60 84 56 78 ori r4,r4,22136 + 1000bc: 54 83 00 20 rlwinm r3,r4,0,0,16 + 1000c0: 4e 80 00 20 blr + +00000000001000c4 : + 1000c4: 54 83 04 3e clrlwi r3,r4,16 + 1000c8: 4e 80 00 20 blr + +00000000001000cc : + 1000cc: 3c 80 12 34 lis r4,4660 + 1000d0: 60 84 56 78 ori r4,r4,22136 + 1000d4: 54 83 04 3e clrlwi r3,r4,16 + 1000d8: 4e 80 00 20 blr + +00000000001000dc : + 1000dc: 54 83 84 3e rlwinm r3,r4,16,16,31 + 1000e0: 4e 80 00 20 blr + +00000000001000e4 : + 1000e4: 3c 80 12 34 lis r4,4660 + 1000e8: 60 84 56 78 ori r4,r4,22136 + 1000ec: 54 83 84 3e rlwinm r3,r4,16,16,31 + 1000f0: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_rlwinm.map b/src/xenia/cpu/frontend/test/bin/instr_rlwinm.map index bd7590f48..308603c61 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_rlwinm.map +++ b/src/xenia/cpu/frontend/test/bin/instr_rlwinm.map @@ -1,10 +1,20 @@ 0000000000000000 t test_rlwinm_extrwi -0000000000000008 t test_rlwinm_1 -0000000000000010 t test_rlwinm_2 -0000000000000018 t test_rlwinm_3 -0000000000000020 t test_rlwinm_4 -0000000000000028 t test_rlwinm_5 -0000000000000030 t test_rlwinm_6 -0000000000000038 t test_rlwinm_7 -0000000000000040 t test_rlwinm_8 -0000000000000048 t test_rlwinm_9 +0000000000000008 t test_rlwinm_extrwi_constant +0000000000000014 t test_rlwinm_1 +000000000000001c t test_rlwinm_1_constant +000000000000002c t test_rlwinm_2 +0000000000000034 t test_rlwinm_2_constant +0000000000000044 t test_rlwinm_3 +000000000000004c t test_rlwinm_3_constant +0000000000000060 t test_rlwinm_4 +0000000000000068 t test_rlwinm_4_constant +000000000000007c t test_rlwinm_5 +0000000000000084 t test_rlwinm_5_constant +0000000000000094 t test_rlwinm_6 +000000000000009c t test_rlwinm_6_constant +00000000000000ac t test_rlwinm_7 +00000000000000b4 t test_rlwinm_7_constant +00000000000000c4 t test_rlwinm_8 +00000000000000cc t test_rlwinm_8_constant +00000000000000dc t test_rlwinm_9 +00000000000000e4 t test_rlwinm_9_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_rlwnm.bin b/src/xenia/cpu/frontend/test/bin/instr_rlwnm.bin index 2f4f2237604efcd3111cab76da8abdd7b9668ccc..8d3bfc9f334858f00e05f0a9342d27d3fa1c51bb 100644 GIT binary patch literal 288 zcma!P){^sUU{J7W5Hd+<39GPJz#tI=6^m)sFhi4Lfr$ZWD~Q|#hJ+RahKd#j1)yFg zm^hHOhRAPVL6ZlI$24nJp_$D969ekC!<2)F0p%31$brRTnsu<~gNR{~6M%_fu}=Xe F1_0%;QEdPK literal 80 qcma!P){^sUU{Hu@)-Z$8R#4g+LTgq*`F2oR0Yd9Q`7l}o%m)C4*cJHz diff --git a/src/xenia/cpu/frontend/test/bin/instr_rlwnm.dis b/src/xenia/cpu/frontend/test/bin/instr_rlwnm.dis index c7910f2be..5cd72c2f0 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_rlwnm.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_rlwnm.dis @@ -4,38 +4,110 @@ Disassembly of section .text: 100000: 5c 83 2a 1e rlwnm r3,r4,r5,8,15 100004: 4e 80 00 20 blr -0000000000100008 : - 100008: 5c 83 28 36 rlwnm r3,r4,r5,0,27 - 10000c: 4e 80 00 20 blr +0000000000100008 : + 100008: 3c 80 12 34 lis r4,4660 + 10000c: 60 84 56 78 ori r4,r4,22136 + 100010: 38 a0 00 18 li r5,24 + 100014: 5c 83 2a 1e rlwnm r3,r4,r5,8,15 + 100018: 4e 80 00 20 blr -0000000000100010 : - 100010: 5c 83 28 3a rlwnm r3,r4,r5,0,29 - 100014: 4e 80 00 20 blr +000000000010001c : + 10001c: 5c 83 28 36 rlwnm r3,r4,r5,0,27 + 100020: 4e 80 00 20 blr -0000000000100018 : - 100018: 5c 83 28 3b rlwnm. r3,r4,r5,0,29 - 10001c: 4e 80 00 20 blr - -0000000000100020 : - 100020: 5c 83 29 7a rlwnm r3,r4,r5,5,29 - 100024: 4e 80 00 20 blr - -0000000000100028 : - 100028: 5c 83 28 3e rotlw r3,r4,r5 - 10002c: 4e 80 00 20 blr - -0000000000100030 : - 100030: 5c 83 28 20 rlwnm r3,r4,r5,0,16 +0000000000100024 : + 100024: 3c 80 12 34 lis r4,4660 + 100028: 60 84 56 78 ori r4,r4,22136 + 10002c: 38 a0 00 04 li r5,4 + 100030: 5c 83 28 36 rlwnm r3,r4,r5,0,27 100034: 4e 80 00 20 blr -0000000000100038 : - 100038: 5c 83 2c 3e rlwnm r3,r4,r5,16,31 +0000000000100038 : + 100038: 5c 83 28 3a rlwnm r3,r4,r5,0,29 10003c: 4e 80 00 20 blr -0000000000100040 : - 100040: 5c 83 2c 3e rlwnm r3,r4,r5,16,31 - 100044: 4e 80 00 20 blr +0000000000100040 : + 100040: 3c 80 90 00 lis r4,-28672 + 100044: 60 84 30 00 ori r4,r4,12288 + 100048: 78 84 00 20 clrldi r4,r4,32 + 10004c: 38 a0 00 02 li r5,2 + 100050: 5c 83 28 3a rlwnm r3,r4,r5,0,29 + 100054: 4e 80 00 20 blr -0000000000100048 : - 100048: 5c 83 28 3e rotlw r3,r4,r5 - 10004c: 4e 80 00 20 blr +0000000000100058 : + 100058: 5c 83 28 3b rlwnm. r3,r4,r5,0,29 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 3c 80 b0 04 lis r4,-20476 + 100064: 60 84 30 00 ori r4,r4,12288 + 100068: 78 84 00 20 clrldi r4,r4,32 + 10006c: 38 a0 00 02 li r5,2 + 100070: 5c 83 28 3b rlwnm. r3,r4,r5,0,29 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 5c 83 29 7a rlwnm r3,r4,r5,5,29 + 10007c: 4e 80 00 20 blr + +0000000000100080 : + 100080: 3c 80 12 34 lis r4,4660 + 100084: 60 84 56 78 ori r4,r4,22136 + 100088: 38 a0 00 00 li r5,0 + 10008c: 5c 83 29 7a rlwnm r3,r4,r5,5,29 + 100090: 4e 80 00 20 blr + +0000000000100094 : + 100094: 5c 83 28 3e rotlw r3,r4,r5 + 100098: 4e 80 00 20 blr + +000000000010009c : + 10009c: 3c 80 12 34 lis r4,4660 + 1000a0: 60 84 56 78 ori r4,r4,22136 + 1000a4: 38 a0 00 00 li r5,0 + 1000a8: 5c 83 28 3e rotlw r3,r4,r5 + 1000ac: 4e 80 00 20 blr + +00000000001000b0 : + 1000b0: 5c 83 28 20 rlwnm r3,r4,r5,0,16 + 1000b4: 4e 80 00 20 blr + +00000000001000b8 : + 1000b8: 3c 80 12 34 lis r4,4660 + 1000bc: 60 84 56 78 ori r4,r4,22136 + 1000c0: 38 a0 00 00 li r5,0 + 1000c4: 5c 83 28 20 rlwnm r3,r4,r5,0,16 + 1000c8: 4e 80 00 20 blr + +00000000001000cc : + 1000cc: 5c 83 2c 3e rlwnm r3,r4,r5,16,31 + 1000d0: 4e 80 00 20 blr + +00000000001000d4 : + 1000d4: 3c 80 12 34 lis r4,4660 + 1000d8: 60 84 56 78 ori r4,r4,22136 + 1000dc: 38 a0 00 00 li r5,0 + 1000e0: 5c 83 2c 3e rlwnm r3,r4,r5,16,31 + 1000e4: 4e 80 00 20 blr + +00000000001000e8 : + 1000e8: 5c 83 2c 3e rlwnm r3,r4,r5,16,31 + 1000ec: 4e 80 00 20 blr + +00000000001000f0 : + 1000f0: 3c 80 12 34 lis r4,4660 + 1000f4: 60 84 56 78 ori r4,r4,22136 + 1000f8: 38 a0 00 10 li r5,16 + 1000fc: 5c 83 2c 3e rlwnm r3,r4,r5,16,31 + 100100: 4e 80 00 20 blr + +0000000000100104 : + 100104: 5c 83 28 3e rotlw r3,r4,r5 + 100108: 4e 80 00 20 blr + +000000000010010c : + 10010c: 3c 80 12 34 lis r4,4660 + 100110: 60 84 56 78 ori r4,r4,22136 + 100114: 38 a0 00 20 li r5,32 + 100118: 5c 83 28 3e rotlw r3,r4,r5 + 10011c: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_rlwnm.map b/src/xenia/cpu/frontend/test/bin/instr_rlwnm.map index 155e01ed1..82c8a80c5 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_rlwnm.map +++ b/src/xenia/cpu/frontend/test/bin/instr_rlwnm.map @@ -1,10 +1,20 @@ 0000000000000000 t test_rlwnm_1 -0000000000000008 t test_rlwnm_2 -0000000000000010 t test_rlwnm_3 -0000000000000018 t test_rlwnm_4 -0000000000000020 t test_rlwnm_5 -0000000000000028 t test_rlwnm_6 -0000000000000030 t test_rlwnm_7 -0000000000000038 t test_rlwnm_8 -0000000000000040 t test_rlwnm_9 -0000000000000048 t test_rlwnm_10 +0000000000000008 t test_rlwnm_1_constant +000000000000001c t test_rlwnm_2 +0000000000000024 t test_rlwnm_2_constant +0000000000000038 t test_rlwnm_3 +0000000000000040 t test_rlwnm_3_constant +0000000000000058 t test_rlwnm_4 +0000000000000060 t test_rlwnm_4_constant +0000000000000078 t test_rlwnm_5 +0000000000000080 t test_rlwnm_5_constant +0000000000000094 t test_rlwnm_6 +000000000000009c t test_rlwnm_6_constant +00000000000000b0 t test_rlwnm_7 +00000000000000b8 t test_rlwnm_7_constant +00000000000000cc t test_rlwnm_8 +00000000000000d4 t test_rlwnm_8_constant +00000000000000e8 t test_rlwnm_9 +00000000000000f0 t test_rlwnm_9_constant +0000000000000104 t test_rlwnm_10 +000000000000010c t test_rlwnm_10_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_sld.bin b/src/xenia/cpu/frontend/test/bin/instr_sld.bin index 029f49b3dfa778c87431e8a0b8ee25141e355975..b61f59d63e64cd6a12cc04f5b4d7d5374bf5f218 100644 GIT binary patch literal 168 zcmb^}!Dy&@I~X5EL&fc3d>9QCcYyI> KG*mnV#s>iP-Z&xv literal 56 Scmb: - 100008: 7c 83 28 36 sld r3,r4,r5 - 10000c: 4e 80 00 20 blr - -0000000000100010 : +0000000000100008 : + 100008: 38 80 00 01 li r4,1 + 10000c: 38 a0 00 00 li r5,0 100010: 7c 83 28 36 sld r3,r4,r5 100014: 4e 80 00 20 blr -0000000000100018 : +0000000000100018 : 100018: 7c 83 28 36 sld r3,r4,r5 10001c: 4e 80 00 20 blr -0000000000100020 : - 100020: 7c 83 28 36 sld r3,r4,r5 - 100024: 4e 80 00 20 blr - -0000000000100028 : +0000000000100020 : + 100020: 38 80 ff ff li r4,-1 + 100024: 38 a0 00 00 li r5,0 100028: 7c 83 28 36 sld r3,r4,r5 10002c: 4e 80 00 20 blr -0000000000100030 : +0000000000100030 : 100030: 7c 83 28 36 sld r3,r4,r5 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 38 80 ff ff li r4,-1 + 10003c: 38 a0 00 01 li r5,1 + 100040: 7c 83 28 36 sld r3,r4,r5 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c 83 28 36 sld r3,r4,r5 + 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 38 80 ff ff li r4,-1 + 100054: 38 a0 00 3e li r5,62 + 100058: 7c 83 28 36 sld r3,r4,r5 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 7c 83 28 36 sld r3,r4,r5 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 38 80 ff ff li r4,-1 + 10006c: 38 a0 00 3f li r5,63 + 100070: 7c 83 28 36 sld r3,r4,r5 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 7c 83 28 36 sld r3,r4,r5 + 10007c: 4e 80 00 20 blr + +0000000000100080 : + 100080: 38 80 ff ff li r4,-1 + 100084: 38 a0 00 40 li r5,64 + 100088: 7c 83 28 36 sld r3,r4,r5 + 10008c: 4e 80 00 20 blr + +0000000000100090 : + 100090: 7c 83 28 36 sld r3,r4,r5 + 100094: 4e 80 00 20 blr + +0000000000100098 : + 100098: 38 80 ff ff li r4,-1 + 10009c: 38 a0 00 64 li r5,100 + 1000a0: 7c 83 28 36 sld r3,r4,r5 + 1000a4: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_sld.map b/src/xenia/cpu/frontend/test/bin/instr_sld.map index 7cc25ae42..454809fb2 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_sld.map +++ b/src/xenia/cpu/frontend/test/bin/instr_sld.map @@ -1,7 +1,14 @@ 0000000000000000 t test_sld_1 -0000000000000008 t test_sld_2 -0000000000000010 t test_sld_3 -0000000000000018 t test_sld_4 -0000000000000020 t test_sld_5 -0000000000000028 t test_sld_6 -0000000000000030 t test_sld_7 +0000000000000008 t test_sld_1_constant +0000000000000018 t test_sld_2 +0000000000000020 t test_sld_2_constant +0000000000000030 t test_sld_3 +0000000000000038 t test_sld_3_constant +0000000000000048 t test_sld_4 +0000000000000050 t test_sld_4_constant +0000000000000060 t test_sld_5 +0000000000000068 t test_sld_5_constant +0000000000000078 t test_sld_6 +0000000000000080 t test_sld_6_constant +0000000000000090 t test_sld_7 +0000000000000098 t test_sld_7_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_slw.bin b/src/xenia/cpu/frontend/test/bin/instr_slw.bin index e27c33b20fdf4ba8287d0fed44b9ce5064e720be..8d4b0bbe680db77a44673125ebb2b0974cf9f632 100644 GIT binary patch literal 216 zcmaKip%K6^48-h3+Q7g5smqoH^N?x=`C!KQk>nUqd=CRCD4x{$|>COlB V4;-rBI8=XesD9v3{luYq!$0kVNF4wG literal 72 Scmb: - 100008: 7c 83 28 30 slw r3,r4,r5 - 10000c: 4e 80 00 20 blr - -0000000000100010 : +0000000000100008 : + 100008: 38 80 00 01 li r4,1 + 10000c: 38 a0 00 00 li r5,0 100010: 7c 83 28 30 slw r3,r4,r5 100014: 4e 80 00 20 blr -0000000000100018 : +0000000000100018 : 100018: 7c 83 28 30 slw r3,r4,r5 10001c: 4e 80 00 20 blr -0000000000100020 : - 100020: 7c 83 28 30 slw r3,r4,r5 - 100024: 4e 80 00 20 blr - -0000000000100028 : +0000000000100020 : + 100020: 38 80 ff ff li r4,-1 + 100024: 38 a0 00 00 li r5,0 100028: 7c 83 28 30 slw r3,r4,r5 10002c: 4e 80 00 20 blr -0000000000100030 : +0000000000100030 : 100030: 7c 83 28 30 slw r3,r4,r5 100034: 4e 80 00 20 blr -0000000000100038 : - 100038: 7c 83 28 30 slw r3,r4,r5 - 10003c: 4e 80 00 20 blr - -0000000000100040 : +0000000000100038 : + 100038: 38 80 ff ff li r4,-1 + 10003c: 38 a0 00 01 li r5,1 100040: 7c 83 28 30 slw r3,r4,r5 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c 83 28 30 slw r3,r4,r5 + 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 38 80 ff ff li r4,-1 + 100054: 38 a0 00 3f li r5,63 + 100058: 7c 83 28 30 slw r3,r4,r5 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 7c 83 28 30 slw r3,r4,r5 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 38 80 ff ff li r4,-1 + 10006c: 38 a0 00 40 li r5,64 + 100070: 7c 83 28 30 slw r3,r4,r5 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 7c 83 28 30 slw r3,r4,r5 + 10007c: 4e 80 00 20 blr + +0000000000100080 : + 100080: 38 80 ff ff li r4,-1 + 100084: 38 a0 00 64 li r5,100 + 100088: 7c 83 28 30 slw r3,r4,r5 + 10008c: 4e 80 00 20 blr + +0000000000100090 : + 100090: 7c 83 28 30 slw r3,r4,r5 + 100094: 4e 80 00 20 blr + +0000000000100098 : + 100098: 38 80 ff ff li r4,-1 + 10009c: 38 a0 00 1e li r5,30 + 1000a0: 7c 83 28 30 slw r3,r4,r5 + 1000a4: 4e 80 00 20 blr + +00000000001000a8 : + 1000a8: 7c 83 28 30 slw r3,r4,r5 + 1000ac: 4e 80 00 20 blr + +00000000001000b0 : + 1000b0: 38 80 ff ff li r4,-1 + 1000b4: 38 a0 00 1f li r5,31 + 1000b8: 7c 83 28 30 slw r3,r4,r5 + 1000bc: 4e 80 00 20 blr + +00000000001000c0 : + 1000c0: 7c 83 28 30 slw r3,r4,r5 + 1000c4: 4e 80 00 20 blr + +00000000001000c8 : + 1000c8: 38 80 ff ff li r4,-1 + 1000cc: 38 a0 00 20 li r5,32 + 1000d0: 7c 83 28 30 slw r3,r4,r5 + 1000d4: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_slw.map b/src/xenia/cpu/frontend/test/bin/instr_slw.map index 911e66b36..3a67a8ae0 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_slw.map +++ b/src/xenia/cpu/frontend/test/bin/instr_slw.map @@ -1,9 +1,18 @@ 0000000000000000 t test_slw_1 -0000000000000008 t test_slw_2 -0000000000000010 t test_slw_3 -0000000000000018 t test_slw_4 -0000000000000020 t test_slw_5 -0000000000000028 t test_slw_6 -0000000000000030 t test_slw_7 -0000000000000038 t test_slw_8 -0000000000000040 t test_slw_9 +0000000000000008 t test_slw_1_constant +0000000000000018 t test_slw_2 +0000000000000020 t test_slw_2_constant +0000000000000030 t test_slw_3 +0000000000000038 t test_slw_3_constant +0000000000000048 t test_slw_4 +0000000000000050 t test_slw_4_constant +0000000000000060 t test_slw_5 +0000000000000068 t test_slw_5_constant +0000000000000078 t test_slw_6 +0000000000000080 t test_slw_6_constant +0000000000000090 t test_slw_7 +0000000000000098 t test_slw_7_constant +00000000000000a8 t test_slw_8 +00000000000000b0 t test_slw_8_constant +00000000000000c0 t test_slw_9 +00000000000000c8 t test_slw_9_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_srad.bin b/src/xenia/cpu/frontend/test/bin/instr_srad.bin index 76656b1f7f484d8747df58a4e6e92b20b78e3429..5bd4470ac74a3f1fb8f71626eaed5071c87c63a9 100644 GIT binary patch literal 224 zcmb: - 10000c: 7c 83 2e 34 srad r3,r4,r5 - 100010: 7c c0 01 14 adde r6,r0,r0 - 100014: 4e 80 00 20 blr +000000000010000c : + 10000c: 38 80 00 01 li r4,1 + 100010: 38 a0 00 00 li r5,0 + 100014: 7c 83 2e 34 srad r3,r4,r5 + 100018: 7c c0 01 14 adde r6,r0,r0 + 10001c: 4e 80 00 20 blr -0000000000100018 : - 100018: 7c 83 2e 34 srad r3,r4,r5 - 10001c: 7c c0 01 14 adde r6,r0,r0 - 100020: 4e 80 00 20 blr +0000000000100020 : + 100020: 7c 83 2e 34 srad r3,r4,r5 + 100024: 7c c0 01 14 adde r6,r0,r0 + 100028: 4e 80 00 20 blr -0000000000100024 : - 100024: 7c 83 2e 34 srad r3,r4,r5 - 100028: 7c c0 01 14 adde r6,r0,r0 - 10002c: 4e 80 00 20 blr +000000000010002c : + 10002c: 38 80 ff ff li r4,-1 + 100030: 38 a0 00 00 li r5,0 + 100034: 7c 83 2e 34 srad r3,r4,r5 + 100038: 7c c0 01 14 adde r6,r0,r0 + 10003c: 4e 80 00 20 blr -0000000000100030 : - 100030: 7c 83 2e 34 srad r3,r4,r5 - 100034: 7c c0 01 14 adde r6,r0,r0 - 100038: 4e 80 00 20 blr +0000000000100040 : + 100040: 7c 83 2e 34 srad r3,r4,r5 + 100044: 7c c0 01 14 adde r6,r0,r0 + 100048: 4e 80 00 20 blr -000000000010003c : - 10003c: 7c 83 2e 34 srad r3,r4,r5 - 100040: 7c c0 01 14 adde r6,r0,r0 - 100044: 4e 80 00 20 blr +000000000010004c : + 10004c: 38 80 ff ff li r4,-1 + 100050: 38 a0 00 01 li r5,1 + 100054: 7c 83 2e 34 srad r3,r4,r5 + 100058: 7c c0 01 14 adde r6,r0,r0 + 10005c: 4e 80 00 20 blr -0000000000100048 : - 100048: 7c 83 2e 34 srad r3,r4,r5 - 10004c: 7c c0 01 14 adde r6,r0,r0 - 100050: 4e 80 00 20 blr +0000000000100060 : + 100060: 7c 83 2e 34 srad r3,r4,r5 + 100064: 7c c0 01 14 adde r6,r0,r0 + 100068: 4e 80 00 20 blr + +000000000010006c : + 10006c: 38 80 ff ff li r4,-1 + 100070: 38 a0 00 3e li r5,62 + 100074: 7c 83 2e 34 srad r3,r4,r5 + 100078: 7c c0 01 14 adde r6,r0,r0 + 10007c: 4e 80 00 20 blr + +0000000000100080 : + 100080: 7c 83 2e 34 srad r3,r4,r5 + 100084: 7c c0 01 14 adde r6,r0,r0 + 100088: 4e 80 00 20 blr + +000000000010008c : + 10008c: 38 80 ff ff li r4,-1 + 100090: 38 a0 00 3f li r5,63 + 100094: 7c 83 2e 34 srad r3,r4,r5 + 100098: 7c c0 01 14 adde r6,r0,r0 + 10009c: 4e 80 00 20 blr + +00000000001000a0 : + 1000a0: 7c 83 2e 34 srad r3,r4,r5 + 1000a4: 7c c0 01 14 adde r6,r0,r0 + 1000a8: 4e 80 00 20 blr + +00000000001000ac : + 1000ac: 38 80 ff ff li r4,-1 + 1000b0: 38 a0 00 40 li r5,64 + 1000b4: 7c 83 2e 34 srad r3,r4,r5 + 1000b8: 7c c0 01 14 adde r6,r0,r0 + 1000bc: 4e 80 00 20 blr + +00000000001000c0 : + 1000c0: 7c 83 2e 34 srad r3,r4,r5 + 1000c4: 7c c0 01 14 adde r6,r0,r0 + 1000c8: 4e 80 00 20 blr + +00000000001000cc : + 1000cc: 38 80 ff ff li r4,-1 + 1000d0: 38 a0 00 64 li r5,100 + 1000d4: 7c 83 2e 34 srad r3,r4,r5 + 1000d8: 7c c0 01 14 adde r6,r0,r0 + 1000dc: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_srad.map b/src/xenia/cpu/frontend/test/bin/instr_srad.map index a4e958547..bf790fbc1 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_srad.map +++ b/src/xenia/cpu/frontend/test/bin/instr_srad.map @@ -1,7 +1,14 @@ 0000000000000000 t test_srad_1 -000000000000000c t test_srad_2 -0000000000000018 t test_srad_3 -0000000000000024 t test_srad_4 -0000000000000030 t test_srad_5 -000000000000003c t test_srad_6 -0000000000000048 t test_srad_7 +000000000000000c t test_srad_1_constant +0000000000000020 t test_srad_2 +000000000000002c t test_srad_2_constant +0000000000000040 t test_srad_3 +000000000000004c t test_srad_3_constant +0000000000000060 t test_srad_4 +000000000000006c t test_srad_4_constant +0000000000000080 t test_srad_5 +000000000000008c t test_srad_5_constant +00000000000000a0 t test_srad_6 +00000000000000ac t test_srad_6_constant +00000000000000c0 t test_srad_7 +00000000000000cc t test_srad_7_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_sradi.bin b/src/xenia/cpu/frontend/test/bin/instr_sradi.bin index e5e0466f31106c84525b8a1b4a9278c657aa0626..2b4fe80deb8e74250a63c83382daa753aa803890 100644 GIT binary patch literal 140 zcmbwzm*}(1j!-zHO>Ff H: - 10000c: 7c 83 06 74 sradi r3,r4,0 - 100010: 7c c0 01 14 adde r6,r0,r0 - 100014: 4e 80 00 20 blr +000000000010000c : + 10000c: 38 80 00 01 li r4,1 + 100010: 7c 83 06 74 sradi r3,r4,0 + 100014: 7c c0 01 14 adde r6,r0,r0 + 100018: 4e 80 00 20 blr -0000000000100018 : - 100018: 7c 83 0e 74 sradi r3,r4,1 - 10001c: 7c c0 01 14 adde r6,r0,r0 - 100020: 4e 80 00 20 blr +000000000010001c : + 10001c: 7c 83 06 74 sradi r3,r4,0 + 100020: 7c c0 01 14 adde r6,r0,r0 + 100024: 4e 80 00 20 blr -0000000000100024 : - 100024: 7c 83 f6 76 sradi r3,r4,62 - 100028: 7c c0 01 14 adde r6,r0,r0 - 10002c: 4e 80 00 20 blr +0000000000100028 : + 100028: 38 80 ff ff li r4,-1 + 10002c: 7c 83 06 74 sradi r3,r4,0 + 100030: 7c c0 01 14 adde r6,r0,r0 + 100034: 4e 80 00 20 blr -0000000000100030 : - 100030: 7c 83 fe 76 sradi r3,r4,63 - 100034: 7c c0 01 14 adde r6,r0,r0 - 100038: 4e 80 00 20 blr +0000000000100038 : + 100038: 7c 83 0e 74 sradi r3,r4,1 + 10003c: 7c c0 01 14 adde r6,r0,r0 + 100040: 4e 80 00 20 blr + +0000000000100044 : + 100044: 38 80 ff ff li r4,-1 + 100048: 7c 83 0e 74 sradi r3,r4,1 + 10004c: 7c c0 01 14 adde r6,r0,r0 + 100050: 4e 80 00 20 blr + +0000000000100054 : + 100054: 7c 83 f6 76 sradi r3,r4,62 + 100058: 7c c0 01 14 adde r6,r0,r0 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 38 80 ff ff li r4,-1 + 100064: 7c 83 f6 76 sradi r3,r4,62 + 100068: 7c c0 01 14 adde r6,r0,r0 + 10006c: 4e 80 00 20 blr + +0000000000100070 : + 100070: 7c 83 fe 76 sradi r3,r4,63 + 100074: 7c c0 01 14 adde r6,r0,r0 + 100078: 4e 80 00 20 blr + +000000000010007c : + 10007c: 38 80 ff ff li r4,-1 + 100080: 7c 83 fe 76 sradi r3,r4,63 + 100084: 7c c0 01 14 adde r6,r0,r0 + 100088: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_sradi.map b/src/xenia/cpu/frontend/test/bin/instr_sradi.map index f06dd5ac8..369313f52 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_sradi.map +++ b/src/xenia/cpu/frontend/test/bin/instr_sradi.map @@ -1,5 +1,10 @@ 0000000000000000 t test_sradi_1 -000000000000000c t test_sradi_2 -0000000000000018 t test_sradi_3 -0000000000000024 t test_sradi_4 -0000000000000030 t test_sradi_5 +000000000000000c t test_sradi_1_constant +000000000000001c t test_sradi_2 +0000000000000028 t test_sradi_2_constant +0000000000000038 t test_sradi_3 +0000000000000044 t test_sradi_3_constant +0000000000000054 t test_sradi_4 +0000000000000060 t test_sradi_4_constant +0000000000000070 t test_sradi_5 +000000000000007c t test_sradi_5_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_sraw.bin b/src/xenia/cpu/frontend/test/bin/instr_sraw.bin index e66cbcd681f90a6423d66615526a43563a93d13c..d5aaed7f92df492ed6c7e5feb777fd86b0dd96d6 100644 GIT binary patch literal 288 zcmbSQ{+#r1b diff --git a/src/xenia/cpu/frontend/test/bin/instr_sraw.dis b/src/xenia/cpu/frontend/test/bin/instr_sraw.dis index 2cffe9c05..76a6bbb77 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_sraw.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_sraw.dis @@ -5,42 +5,105 @@ Disassembly of section .text: 100004: 7c c0 01 14 adde r6,r0,r0 100008: 4e 80 00 20 blr -000000000010000c : - 10000c: 7c 83 2e 30 sraw r3,r4,r5 - 100010: 7c c0 01 14 adde r6,r0,r0 - 100014: 4e 80 00 20 blr +000000000010000c : + 10000c: 38 80 00 01 li r4,1 + 100010: 38 a0 00 00 li r5,0 + 100014: 7c 83 2e 30 sraw r3,r4,r5 + 100018: 7c c0 01 14 adde r6,r0,r0 + 10001c: 4e 80 00 20 blr -0000000000100018 : - 100018: 7c 83 2e 30 sraw r3,r4,r5 - 10001c: 7c c0 01 14 adde r6,r0,r0 - 100020: 4e 80 00 20 blr +0000000000100020 : + 100020: 7c 83 2e 30 sraw r3,r4,r5 + 100024: 7c c0 01 14 adde r6,r0,r0 + 100028: 4e 80 00 20 blr -0000000000100024 : - 100024: 7c 83 2e 30 sraw r3,r4,r5 - 100028: 7c c0 01 14 adde r6,r0,r0 - 10002c: 4e 80 00 20 blr +000000000010002c : + 10002c: 38 80 ff ff li r4,-1 + 100030: 38 a0 00 00 li r5,0 + 100034: 7c 83 2e 30 sraw r3,r4,r5 + 100038: 7c c0 01 14 adde r6,r0,r0 + 10003c: 4e 80 00 20 blr -0000000000100030 : - 100030: 7c 83 2e 30 sraw r3,r4,r5 - 100034: 7c c0 01 14 adde r6,r0,r0 - 100038: 4e 80 00 20 blr +0000000000100040 : + 100040: 7c 83 2e 30 sraw r3,r4,r5 + 100044: 7c c0 01 14 adde r6,r0,r0 + 100048: 4e 80 00 20 blr -000000000010003c : - 10003c: 7c 83 2e 30 sraw r3,r4,r5 - 100040: 7c c0 01 14 adde r6,r0,r0 - 100044: 4e 80 00 20 blr - -0000000000100048 : - 100048: 7c 83 2e 30 sraw r3,r4,r5 - 10004c: 7c c0 01 14 adde r6,r0,r0 - 100050: 4e 80 00 20 blr - -0000000000100054 : +000000000010004c : + 10004c: 38 80 ff ff li r4,-1 + 100050: 38 a0 00 01 li r5,1 100054: 7c 83 2e 30 sraw r3,r4,r5 100058: 7c c0 01 14 adde r6,r0,r0 10005c: 4e 80 00 20 blr -0000000000100060 : +0000000000100060 : 100060: 7c 83 2e 30 sraw r3,r4,r5 100064: 7c c0 01 14 adde r6,r0,r0 100068: 4e 80 00 20 blr + +000000000010006c : + 10006c: 38 80 ff ff li r4,-1 + 100070: 38 a0 00 3f li r5,63 + 100074: 7c 83 2e 30 sraw r3,r4,r5 + 100078: 7c c0 01 14 adde r6,r0,r0 + 10007c: 4e 80 00 20 blr + +0000000000100080 : + 100080: 7c 83 2e 30 sraw r3,r4,r5 + 100084: 7c c0 01 14 adde r6,r0,r0 + 100088: 4e 80 00 20 blr + +000000000010008c : + 10008c: 38 80 ff ff li r4,-1 + 100090: 38 a0 00 40 li r5,64 + 100094: 7c 83 2e 30 sraw r3,r4,r5 + 100098: 7c c0 01 14 adde r6,r0,r0 + 10009c: 4e 80 00 20 blr + +00000000001000a0 : + 1000a0: 7c 83 2e 30 sraw r3,r4,r5 + 1000a4: 7c c0 01 14 adde r6,r0,r0 + 1000a8: 4e 80 00 20 blr + +00000000001000ac : + 1000ac: 38 80 ff ff li r4,-1 + 1000b0: 38 a0 00 64 li r5,100 + 1000b4: 7c 83 2e 30 sraw r3,r4,r5 + 1000b8: 7c c0 01 14 adde r6,r0,r0 + 1000bc: 4e 80 00 20 blr + +00000000001000c0 : + 1000c0: 7c 83 2e 30 sraw r3,r4,r5 + 1000c4: 7c c0 01 14 adde r6,r0,r0 + 1000c8: 4e 80 00 20 blr + +00000000001000cc : + 1000cc: 38 80 ff ff li r4,-1 + 1000d0: 38 a0 00 1e li r5,30 + 1000d4: 7c 83 2e 30 sraw r3,r4,r5 + 1000d8: 7c c0 01 14 adde r6,r0,r0 + 1000dc: 4e 80 00 20 blr + +00000000001000e0 : + 1000e0: 7c 83 2e 30 sraw r3,r4,r5 + 1000e4: 7c c0 01 14 adde r6,r0,r0 + 1000e8: 4e 80 00 20 blr + +00000000001000ec : + 1000ec: 38 80 ff ff li r4,-1 + 1000f0: 38 a0 00 1f li r5,31 + 1000f4: 7c 83 2e 30 sraw r3,r4,r5 + 1000f8: 7c c0 01 14 adde r6,r0,r0 + 1000fc: 4e 80 00 20 blr + +0000000000100100 : + 100100: 7c 83 2e 30 sraw r3,r4,r5 + 100104: 7c c0 01 14 adde r6,r0,r0 + 100108: 4e 80 00 20 blr + +000000000010010c : + 10010c: 38 80 ff ff li r4,-1 + 100110: 38 a0 00 20 li r5,32 + 100114: 7c 83 2e 30 sraw r3,r4,r5 + 100118: 7c c0 01 14 adde r6,r0,r0 + 10011c: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_sraw.map b/src/xenia/cpu/frontend/test/bin/instr_sraw.map index b932d9501..981396355 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_sraw.map +++ b/src/xenia/cpu/frontend/test/bin/instr_sraw.map @@ -1,9 +1,18 @@ 0000000000000000 t test_sraw_1 -000000000000000c t test_sraw_2 -0000000000000018 t test_sraw_3 -0000000000000024 t test_sraw_4 -0000000000000030 t test_sraw_5 -000000000000003c t test_sraw_6 -0000000000000048 t test_sraw_7 -0000000000000054 t test_sraw_8 -0000000000000060 t test_sraw_9 +000000000000000c t test_sraw_1_constant +0000000000000020 t test_sraw_2 +000000000000002c t test_sraw_2_constant +0000000000000040 t test_sraw_3 +000000000000004c t test_sraw_3_constant +0000000000000060 t test_sraw_4 +000000000000006c t test_sraw_4_constant +0000000000000080 t test_sraw_5 +000000000000008c t test_sraw_5_constant +00000000000000a0 t test_sraw_6 +00000000000000ac t test_sraw_6_constant +00000000000000c0 t test_sraw_7 +00000000000000cc t test_sraw_7_constant +00000000000000e0 t test_sraw_8 +00000000000000ec t test_sraw_8_constant +0000000000000100 t test_sraw_9 +000000000000010c t test_sraw_9_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_srawi.bin b/src/xenia/cpu/frontend/test/bin/instr_srawi.bin index d050827549fd6358ef61b60285bf53db2f89efbd..cdb24b97df6eb6e01db30f9b889287249c5ffbf0 100644 GIT binary patch literal 140 zcmbwzoE$?_%+S{(Bu$& E0F(wadH?_b literal 60 fcmb: - 10000c: 7c 83 06 70 srawi r3,r4,0 - 100010: 7c c0 01 14 adde r6,r0,r0 - 100014: 4e 80 00 20 blr +000000000010000c : + 10000c: 38 80 00 01 li r4,1 + 100010: 7c 83 06 70 srawi r3,r4,0 + 100014: 7c c0 01 14 adde r6,r0,r0 + 100018: 4e 80 00 20 blr -0000000000100018 : - 100018: 7c 83 0e 70 srawi r3,r4,1 - 10001c: 7c c0 01 14 adde r6,r0,r0 - 100020: 4e 80 00 20 blr +000000000010001c : + 10001c: 7c 83 06 70 srawi r3,r4,0 + 100020: 7c c0 01 14 adde r6,r0,r0 + 100024: 4e 80 00 20 blr -0000000000100024 : - 100024: 7c 83 f6 70 srawi r3,r4,30 - 100028: 7c c0 01 14 adde r6,r0,r0 - 10002c: 4e 80 00 20 blr +0000000000100028 : + 100028: 38 80 ff ff li r4,-1 + 10002c: 7c 83 06 70 srawi r3,r4,0 + 100030: 7c c0 01 14 adde r6,r0,r0 + 100034: 4e 80 00 20 blr -0000000000100030 : - 100030: 7c 83 fe 70 srawi r3,r4,31 - 100034: 7c c0 01 14 adde r6,r0,r0 - 100038: 4e 80 00 20 blr +0000000000100038 : + 100038: 7c 83 0e 70 srawi r3,r4,1 + 10003c: 7c c0 01 14 adde r6,r0,r0 + 100040: 4e 80 00 20 blr + +0000000000100044 : + 100044: 38 80 ff ff li r4,-1 + 100048: 7c 83 0e 70 srawi r3,r4,1 + 10004c: 7c c0 01 14 adde r6,r0,r0 + 100050: 4e 80 00 20 blr + +0000000000100054 : + 100054: 7c 83 f6 70 srawi r3,r4,30 + 100058: 7c c0 01 14 adde r6,r0,r0 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 38 80 ff ff li r4,-1 + 100064: 7c 83 f6 70 srawi r3,r4,30 + 100068: 7c c0 01 14 adde r6,r0,r0 + 10006c: 4e 80 00 20 blr + +0000000000100070 : + 100070: 7c 83 fe 70 srawi r3,r4,31 + 100074: 7c c0 01 14 adde r6,r0,r0 + 100078: 4e 80 00 20 blr + +000000000010007c : + 10007c: 38 80 ff ff li r4,-1 + 100080: 7c 83 fe 70 srawi r3,r4,31 + 100084: 7c c0 01 14 adde r6,r0,r0 + 100088: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_srawi.map b/src/xenia/cpu/frontend/test/bin/instr_srawi.map index 6f4af09e8..a74cbf16d 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_srawi.map +++ b/src/xenia/cpu/frontend/test/bin/instr_srawi.map @@ -1,5 +1,10 @@ 0000000000000000 t test_srawi_1 -000000000000000c t test_srawi_2 -0000000000000018 t test_srawi_3 -0000000000000024 t test_srawi_4 -0000000000000030 t test_srawi_5 +000000000000000c t test_srawi_1_constant +000000000000001c t test_srawi_2 +0000000000000028 t test_srawi_2_constant +0000000000000038 t test_srawi_3 +0000000000000044 t test_srawi_3_constant +0000000000000054 t test_srawi_4 +0000000000000060 t test_srawi_4_constant +0000000000000070 t test_srawi_5 +000000000000007c t test_srawi_5_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_srd.bin b/src/xenia/cpu/frontend/test/bin/instr_srd.bin index cee9f21e5790f48f7ba021ac091ef5ac9ae2bce9..c916eac78affdef618e5eaf10a6bf93bf166e3d3 100644 GIT binary patch literal 168 zcmb^}!Dy&@I~X5EL&fc3d>9QCcYyI> KG*mnV#s>fhy*OF` literal 56 Scmb: - 100008: 7c 83 2c 36 srd r3,r4,r5 - 10000c: 4e 80 00 20 blr - -0000000000100010 : +0000000000100008 : + 100008: 38 80 00 01 li r4,1 + 10000c: 38 a0 00 00 li r5,0 100010: 7c 83 2c 36 srd r3,r4,r5 100014: 4e 80 00 20 blr -0000000000100018 : +0000000000100018 : 100018: 7c 83 2c 36 srd r3,r4,r5 10001c: 4e 80 00 20 blr -0000000000100020 : - 100020: 7c 83 2c 36 srd r3,r4,r5 - 100024: 4e 80 00 20 blr - -0000000000100028 : +0000000000100020 : + 100020: 38 80 ff ff li r4,-1 + 100024: 38 a0 00 00 li r5,0 100028: 7c 83 2c 36 srd r3,r4,r5 10002c: 4e 80 00 20 blr -0000000000100030 : +0000000000100030 : 100030: 7c 83 2c 36 srd r3,r4,r5 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 38 80 ff ff li r4,-1 + 10003c: 38 a0 00 01 li r5,1 + 100040: 7c 83 2c 36 srd r3,r4,r5 + 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c 83 2c 36 srd r3,r4,r5 + 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 38 80 ff ff li r4,-1 + 100054: 38 a0 00 3e li r5,62 + 100058: 7c 83 2c 36 srd r3,r4,r5 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 7c 83 2c 36 srd r3,r4,r5 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 38 80 ff ff li r4,-1 + 10006c: 38 a0 00 3f li r5,63 + 100070: 7c 83 2c 36 srd r3,r4,r5 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 7c 83 2c 36 srd r3,r4,r5 + 10007c: 4e 80 00 20 blr + +0000000000100080 : + 100080: 38 80 ff ff li r4,-1 + 100084: 38 a0 00 40 li r5,64 + 100088: 7c 83 2c 36 srd r3,r4,r5 + 10008c: 4e 80 00 20 blr + +0000000000100090 : + 100090: 7c 83 2c 36 srd r3,r4,r5 + 100094: 4e 80 00 20 blr + +0000000000100098 : + 100098: 38 80 ff ff li r4,-1 + 10009c: 38 a0 00 64 li r5,100 + 1000a0: 7c 83 2c 36 srd r3,r4,r5 + 1000a4: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_srd.map b/src/xenia/cpu/frontend/test/bin/instr_srd.map index 0febab071..ba046b105 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_srd.map +++ b/src/xenia/cpu/frontend/test/bin/instr_srd.map @@ -1,7 +1,14 @@ 0000000000000000 t test_srd_1 -0000000000000008 t test_srd_2 -0000000000000010 t test_srd_3 -0000000000000018 t test_srd_4 -0000000000000020 t test_srd_5 -0000000000000028 t test_srd_6 -0000000000000030 t test_srd_7 +0000000000000008 t test_srd_1_constant +0000000000000018 t test_srd_2 +0000000000000020 t test_srd_2_constant +0000000000000030 t test_srd_3 +0000000000000038 t test_srd_3_constant +0000000000000048 t test_srd_4 +0000000000000050 t test_srd_4_constant +0000000000000060 t test_srd_5 +0000000000000068 t test_srd_5_constant +0000000000000078 t test_srd_6 +0000000000000080 t test_srd_6_constant +0000000000000090 t test_srd_7 +0000000000000098 t test_srd_7_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_srw.bin b/src/xenia/cpu/frontend/test/bin/instr_srw.bin index 952c4ba31005421baf840a7afc2775c63a912cf4..5e7ee49b9806744292016cefbb61dcccbdb755e9 100644 GIT binary patch literal 216 zcmb^}!Dy&@dl(-^L&Y6nd>9QCPl54a WG*ny;#)r{Rad{XYMnlCFV0-`!f=Fcm literal 72 Scmb: - 100008: 7c 83 2c 30 srw r3,r4,r5 - 10000c: 4e 80 00 20 blr - -0000000000100010 : +0000000000100008 : + 100008: 38 80 00 01 li r4,1 + 10000c: 38 a0 00 00 li r5,0 100010: 7c 83 2c 30 srw r3,r4,r5 100014: 4e 80 00 20 blr -0000000000100018 : +0000000000100018 : 100018: 7c 83 2c 30 srw r3,r4,r5 10001c: 4e 80 00 20 blr -0000000000100020 : - 100020: 7c 83 2c 30 srw r3,r4,r5 - 100024: 4e 80 00 20 blr - -0000000000100028 : +0000000000100020 : + 100020: 38 80 ff ff li r4,-1 + 100024: 38 a0 00 00 li r5,0 100028: 7c 83 2c 30 srw r3,r4,r5 10002c: 4e 80 00 20 blr -0000000000100030 : +0000000000100030 : 100030: 7c 83 2c 30 srw r3,r4,r5 100034: 4e 80 00 20 blr -0000000000100038 : - 100038: 7c 83 2c 30 srw r3,r4,r5 - 10003c: 4e 80 00 20 blr - -0000000000100040 : +0000000000100038 : + 100038: 38 80 ff ff li r4,-1 + 10003c: 38 a0 00 01 li r5,1 100040: 7c 83 2c 30 srw r3,r4,r5 100044: 4e 80 00 20 blr + +0000000000100048 : + 100048: 7c 83 2c 30 srw r3,r4,r5 + 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 38 80 ff ff li r4,-1 + 100054: 38 a0 00 3f li r5,63 + 100058: 7c 83 2c 30 srw r3,r4,r5 + 10005c: 4e 80 00 20 blr + +0000000000100060 : + 100060: 7c 83 2c 30 srw r3,r4,r5 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 38 80 ff ff li r4,-1 + 10006c: 38 a0 00 40 li r5,64 + 100070: 7c 83 2c 30 srw r3,r4,r5 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 7c 83 2c 30 srw r3,r4,r5 + 10007c: 4e 80 00 20 blr + +0000000000100080 : + 100080: 38 80 ff ff li r4,-1 + 100084: 38 a0 00 64 li r5,100 + 100088: 7c 83 2c 30 srw r3,r4,r5 + 10008c: 4e 80 00 20 blr + +0000000000100090 : + 100090: 7c 83 2c 30 srw r3,r4,r5 + 100094: 4e 80 00 20 blr + +0000000000100098 : + 100098: 38 80 ff ff li r4,-1 + 10009c: 38 a0 00 1e li r5,30 + 1000a0: 7c 83 2c 30 srw r3,r4,r5 + 1000a4: 4e 80 00 20 blr + +00000000001000a8 : + 1000a8: 7c 83 2c 30 srw r3,r4,r5 + 1000ac: 4e 80 00 20 blr + +00000000001000b0 : + 1000b0: 38 80 ff ff li r4,-1 + 1000b4: 38 a0 00 1f li r5,31 + 1000b8: 7c 83 2c 30 srw r3,r4,r5 + 1000bc: 4e 80 00 20 blr + +00000000001000c0 : + 1000c0: 7c 83 2c 30 srw r3,r4,r5 + 1000c4: 4e 80 00 20 blr + +00000000001000c8 : + 1000c8: 38 80 ff ff li r4,-1 + 1000cc: 38 a0 00 20 li r5,32 + 1000d0: 7c 83 2c 30 srw r3,r4,r5 + 1000d4: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_srw.map b/src/xenia/cpu/frontend/test/bin/instr_srw.map index 5ba1b866b..7a2069395 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_srw.map +++ b/src/xenia/cpu/frontend/test/bin/instr_srw.map @@ -1,9 +1,18 @@ 0000000000000000 t test_srw_1 -0000000000000008 t test_srw_2 -0000000000000010 t test_srw_3 -0000000000000018 t test_srw_4 -0000000000000020 t test_srw_5 -0000000000000028 t test_srw_6 -0000000000000030 t test_srw_7 -0000000000000038 t test_srw_8 -0000000000000040 t test_srw_9 +0000000000000008 t test_srw_1_constant +0000000000000018 t test_srw_2 +0000000000000020 t test_srw_2_constant +0000000000000030 t test_srw_3 +0000000000000038 t test_srw_3_constant +0000000000000048 t test_srw_4 +0000000000000050 t test_srw_4_constant +0000000000000060 t test_srw_5 +0000000000000068 t test_srw_5_constant +0000000000000078 t test_srw_6 +0000000000000080 t test_srw_6_constant +0000000000000090 t test_srw_7 +0000000000000098 t test_srw_7_constant +00000000000000a8 t test_srw_8 +00000000000000b0 t test_srw_8_constant +00000000000000c0 t test_srw_9 +00000000000000c8 t test_srw_9_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_stvew.bin b/src/xenia/cpu/frontend/test/bin/instr_stvew.bin index ceea4226bb3e0bd383cf67a7911af06c19c0a59d..b454951ce1b8c29a9d770cbab236df2cd9643e69 100644 GIT binary patch literal 80 ocmbz>% literal 32 Scmb: - 100008: 7c 60 21 8e stvewx v3,0,r4 - 10000c: 4e 80 00 20 blr +0000000000100008 : + 100008: 38 80 10 50 li r4,4176 + 10000c: 7c 60 21 8e stvewx v3,0,r4 + 100010: 4e 80 00 20 blr -0000000000100010 : - 100010: 7c 60 21 8e stvewx v3,0,r4 - 100014: 4e 80 00 20 blr +0000000000100014 : + 100014: 7c 60 21 8e stvewx v3,0,r4 + 100018: 4e 80 00 20 blr -0000000000100018 : - 100018: 7c 60 21 8e stvewx v3,0,r4 - 10001c: 4e 80 00 20 blr +000000000010001c : + 10001c: 38 80 10 54 li r4,4180 + 100020: 7c 60 21 8e stvewx v3,0,r4 + 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 7c 60 21 8e stvewx v3,0,r4 + 10002c: 4e 80 00 20 blr + +0000000000100030 : + 100030: 38 80 10 58 li r4,4184 + 100034: 7c 60 21 8e stvewx v3,0,r4 + 100038: 4e 80 00 20 blr + +000000000010003c : + 10003c: 7c 60 21 8e stvewx v3,0,r4 + 100040: 4e 80 00 20 blr + +0000000000100044 : + 100044: 38 80 10 5c li r4,4188 + 100048: 7c 60 21 8e stvewx v3,0,r4 + 10004c: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_stvew.map b/src/xenia/cpu/frontend/test/bin/instr_stvew.map index 7a317bfbf..6129dde95 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_stvew.map +++ b/src/xenia/cpu/frontend/test/bin/instr_stvew.map @@ -1,4 +1,8 @@ 0000000000000000 t test_stvew_1 -0000000000000008 t test_stvew_2 -0000000000000010 t test_stvew_3 -0000000000000018 t test_stvew_4 +0000000000000008 t test_stvew_1_constant +0000000000000014 t test_stvew_2 +000000000000001c t test_stvew_2_constant +0000000000000028 t test_stvew_3 +0000000000000030 t test_stvew_3_constant +000000000000003c t test_stvew_4 +0000000000000044 t test_stvew_4_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_stvl.bin b/src/xenia/cpu/frontend/test/bin/instr_stvl.bin index 4ec644997db0d107310e362f142152e1c69b65e3..19385e1c65879ba3fd6e7b8d77b5662cc9bd91e3 100644 GIT binary patch literal 40 ccmb: - 100008: 7c 64 05 0e stvlx v3,r4,r0 - 10000c: 4e 80 00 20 blr +0000000000100008 : + 100008: 38 80 10 40 li r4,4160 + 10000c: 7c 64 05 0e stvlx v3,r4,r0 + 100010: 4e 80 00 20 blr + +0000000000100014 : + 100014: 7c 64 05 0e stvlx v3,r4,r0 + 100018: 4e 80 00 20 blr + +000000000010001c : + 10001c: 38 80 10 44 li r4,4164 + 100020: 7c 64 05 0e stvlx v3,r4,r0 + 100024: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_stvl.map b/src/xenia/cpu/frontend/test/bin/instr_stvl.map index e4549f6e4..71441d4ff 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_stvl.map +++ b/src/xenia/cpu/frontend/test/bin/instr_stvl.map @@ -1,2 +1,4 @@ 0000000000000000 t test_stvl_1 -0000000000000008 t test_stvl_2 +0000000000000008 t test_stvl_1_constant +0000000000000014 t test_stvl_2 +000000000000001c t test_stvl_2_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_stvr.bin b/src/xenia/cpu/frontend/test/bin/instr_stvr.bin index 4e8fde8776955572edc410c379159a5a66705b2e..e16bd4c3fd550053c7eb72b4ebb4e163f545c03f 100644 GIT binary patch literal 44 hcmb: - 100008: 7c 64 05 4e stvrx v3,r4,r0 - 10000c: 4e 80 00 20 blr +0000000000100008 : + 100008: 38 80 10 40 li r4,4160 + 10000c: 38 a0 00 10 li r5,16 + 100010: 7c 64 2d 4e stvrx v3,r4,r5 + 100014: 4e 80 00 20 blr + +0000000000100018 : + 100018: 7c 64 05 4e stvrx v3,r4,r0 + 10001c: 4e 80 00 20 blr + +0000000000100020 : + 100020: 38 80 10 44 li r4,4164 + 100024: 7c 64 05 4e stvrx v3,r4,r0 + 100028: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_stvr.map b/src/xenia/cpu/frontend/test/bin/instr_stvr.map index 4d82bf66b..10975d1a4 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_stvr.map +++ b/src/xenia/cpu/frontend/test/bin/instr_stvr.map @@ -1,2 +1,4 @@ 0000000000000000 t test_stvr_1 -0000000000000008 t test_stvr_2 +0000000000000008 t test_stvr_1_constant +0000000000000018 t test_stvr_2 +0000000000000020 t test_stvr_2_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_subf.bin b/src/xenia/cpu/frontend/test/bin/instr_subf.bin index 1c82452493d5506d37f396cc1a4795c6e7c62317..f5c18bd14f210588b2506617c6fe7db92d14d457 100644 GIT binary patch literal 128 zcmb=)iU{y)U{J7iU|>x2V%~3?0Hm{-57a=#VYH: - 100008: 7c 6a 58 50 subf r3,r10,r11 - 10000c: 4e 80 00 20 blr - -0000000000100010 : - 100010: 7c 6a 58 50 subf r3,r10,r11 - 100014: 4e 80 00 20 blr - -0000000000100018 : +0000000000100008 : + 100008: 3d 40 00 01 lis r10,1 + 10000c: 61 4a 03 bf ori r10,r10,959 + 100010: 3d 60 00 01 lis r11,1 + 100014: 61 6b 03 c0 ori r11,r11,960 100018: 7c 6a 58 50 subf r3,r10,r11 10001c: 4e 80 00 20 blr -0000000000100020 : +0000000000100020 : 100020: 7c 6a 58 50 subf r3,r10,r11 100024: 4e 80 00 20 blr + +0000000000100028 : + 100028: 39 40 00 00 li r10,0 + 10002c: 39 60 00 00 li r11,0 + 100030: 7c 6a 58 50 subf r3,r10,r11 + 100034: 4e 80 00 20 blr + +0000000000100038 : + 100038: 7c 6a 58 50 subf r3,r10,r11 + 10003c: 4e 80 00 20 blr + +0000000000100040 : + 100040: 39 40 00 01 li r10,1 + 100044: 39 60 00 00 li r11,0 + 100048: 7c 6a 58 50 subf r3,r10,r11 + 10004c: 4e 80 00 20 blr + +0000000000100050 : + 100050: 7c 6a 58 50 subf r3,r10,r11 + 100054: 4e 80 00 20 blr + +0000000000100058 : + 100058: 39 40 00 00 li r10,0 + 10005c: 39 60 00 01 li r11,1 + 100060: 7c 6a 58 50 subf r3,r10,r11 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 7c 6a 58 50 subf r3,r10,r11 + 10006c: 4e 80 00 20 blr + +0000000000100070 : + 100070: 39 40 ff ff li r10,-1 + 100074: 39 60 ff ff li r11,-1 + 100078: 7c 6a 58 50 subf r3,r10,r11 + 10007c: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_subf.map b/src/xenia/cpu/frontend/test/bin/instr_subf.map index 68d80a007..366b51ba1 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_subf.map +++ b/src/xenia/cpu/frontend/test/bin/instr_subf.map @@ -1,5 +1,10 @@ 0000000000000000 t test_subf_1 -0000000000000008 t test_subf_2 -0000000000000010 t test_subf_3 -0000000000000018 t test_subf_4 -0000000000000020 t test_subf_5 +0000000000000008 t test_subf_1_constant +0000000000000020 t test_subf_2 +0000000000000028 t test_subf_2_constant +0000000000000038 t test_subf_3 +0000000000000040 t test_subf_3_constant +0000000000000050 t test_subf_4 +0000000000000058 t test_subf_4_constant +0000000000000068 t test_subf_5 +0000000000000070 t test_subf_5_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_subfc.bin b/src/xenia/cpu/frontend/test/bin/instr_subfc.bin index fb8a7f3bb0d0b8a02726c0592fb4caec1dd3fe39..e4ffb61a0f6e561dbab1f82d142802d0d77f2fcb 100644 GIT binary patch literal 168 zcmb=)iV&!2U=;CdU{J7iU|>x2V%~3?0Hm{-57Z#ZA+s$V7#J)Q7#NVnkl8?aMgsC6 V{fx+ZklB_F|NmPi{Qr+E1^`hiEnxrv literal 60 Wcmb=)iV&!2U=;CdU{I(bkqrO|au9+5 diff --git a/src/xenia/cpu/frontend/test/bin/instr_subfc.dis b/src/xenia/cpu/frontend/test/bin/instr_subfc.dis index 796f30e3c..4077c5fb4 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_subfc.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_subfc.dis @@ -5,22 +5,59 @@ Disassembly of section .text: 100004: 7c 80 01 14 adde r4,r0,r0 100008: 4e 80 00 20 blr -000000000010000c : - 10000c: 7c 6a 58 10 subfc r3,r10,r11 - 100010: 7c 80 01 14 adde r4,r0,r0 - 100014: 4e 80 00 20 blr +000000000010000c : + 10000c: 3d 40 00 01 lis r10,1 + 100010: 61 4a 03 bf ori r10,r10,959 + 100014: 3d 60 00 01 lis r11,1 + 100018: 61 6b 03 c0 ori r11,r11,960 + 10001c: 7c 6a 58 10 subfc r3,r10,r11 + 100020: 7c 80 01 14 adde r4,r0,r0 + 100024: 4e 80 00 20 blr -0000000000100018 : - 100018: 7c 6a 58 10 subfc r3,r10,r11 - 10001c: 7c 80 01 14 adde r4,r0,r0 - 100020: 4e 80 00 20 blr +0000000000100028 : + 100028: 7c 6a 58 10 subfc r3,r10,r11 + 10002c: 7c 80 01 14 adde r4,r0,r0 + 100030: 4e 80 00 20 blr -0000000000100024 : - 100024: 7c 6a 58 10 subfc r3,r10,r11 - 100028: 7c 80 01 14 adde r4,r0,r0 - 10002c: 4e 80 00 20 blr +0000000000100034 : + 100034: 39 40 00 00 li r10,0 + 100038: 39 60 00 00 li r11,0 + 10003c: 7c 6a 58 10 subfc r3,r10,r11 + 100040: 7c 80 01 14 adde r4,r0,r0 + 100044: 4e 80 00 20 blr -0000000000100030 : - 100030: 7c 6a 58 10 subfc r3,r10,r11 - 100034: 7c 80 01 14 adde r4,r0,r0 - 100038: 4e 80 00 20 blr +0000000000100048 : + 100048: 7c 6a 58 10 subfc r3,r10,r11 + 10004c: 7c 80 01 14 adde r4,r0,r0 + 100050: 4e 80 00 20 blr + +0000000000100054 : + 100054: 39 40 00 01 li r10,1 + 100058: 39 60 00 00 li r11,0 + 10005c: 7c 6a 58 10 subfc r3,r10,r11 + 100060: 7c 80 01 14 adde r4,r0,r0 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 7c 6a 58 10 subfc r3,r10,r11 + 10006c: 7c 80 01 14 adde r4,r0,r0 + 100070: 4e 80 00 20 blr + +0000000000100074 : + 100074: 39 40 00 00 li r10,0 + 100078: 39 60 00 01 li r11,1 + 10007c: 7c 6a 58 10 subfc r3,r10,r11 + 100080: 7c 80 01 14 adde r4,r0,r0 + 100084: 4e 80 00 20 blr + +0000000000100088 : + 100088: 7c 6a 58 10 subfc r3,r10,r11 + 10008c: 7c 80 01 14 adde r4,r0,r0 + 100090: 4e 80 00 20 blr + +0000000000100094 : + 100094: 39 40 ff ff li r10,-1 + 100098: 39 60 ff ff li r11,-1 + 10009c: 7c 6a 58 10 subfc r3,r10,r11 + 1000a0: 7c 80 01 14 adde r4,r0,r0 + 1000a4: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_subfc.map b/src/xenia/cpu/frontend/test/bin/instr_subfc.map index 073f8bc6b..59fb01d69 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_subfc.map +++ b/src/xenia/cpu/frontend/test/bin/instr_subfc.map @@ -1,5 +1,10 @@ 0000000000000000 t test_subfc_1 -000000000000000c t test_subfc_2 -0000000000000018 t test_subfc_3 -0000000000000024 t test_subfc_4 -0000000000000030 t test_subfc_5 +000000000000000c t test_subfc_1_constant +0000000000000028 t test_subfc_2 +0000000000000034 t test_subfc_2_constant +0000000000000048 t test_subfc_3 +0000000000000054 t test_subfc_3_constant +0000000000000068 t test_subfc_4 +0000000000000074 t test_subfc_4_constant +0000000000000088 t test_subfc_5 +0000000000000094 t test_subfc_5_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_subfe.bin b/src/xenia/cpu/frontend/test/bin/instr_subfe.bin index ec01e667c8e75d8fc5ccc21ad0561c372a15acf9..423ed2c972b5bdca3efca2904184e24efeb83664 100644 GIT binary patch literal 168 zcmb=)iWI16U=;CdU{J7iU|>x2V%~3?0Hm{-57Z#ZA+s$V7#J)Q7#NVnkl8?aMgsC6 V{fx+ZklB_F|NmPi{Qr+E1^`rgEo%S( literal 60 Wcmb=)iWI16U=;CdU{I(bkqrO}91w>9 diff --git a/src/xenia/cpu/frontend/test/bin/instr_subfe.dis b/src/xenia/cpu/frontend/test/bin/instr_subfe.dis index dc0a65b85..48bec473a 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_subfe.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_subfe.dis @@ -5,22 +5,59 @@ Disassembly of section .text: 100004: 7c 80 01 14 adde r4,r0,r0 100008: 4e 80 00 20 blr -000000000010000c : - 10000c: 7c 6a 59 10 subfe r3,r10,r11 - 100010: 7c 80 01 14 adde r4,r0,r0 - 100014: 4e 80 00 20 blr +000000000010000c : + 10000c: 3d 40 00 01 lis r10,1 + 100010: 61 4a 03 bf ori r10,r10,959 + 100014: 3d 60 00 01 lis r11,1 + 100018: 61 6b 03 c0 ori r11,r11,960 + 10001c: 7c 6a 59 10 subfe r3,r10,r11 + 100020: 7c 80 01 14 adde r4,r0,r0 + 100024: 4e 80 00 20 blr -0000000000100018 : - 100018: 7c 6a 59 10 subfe r3,r10,r11 - 10001c: 7c 80 01 14 adde r4,r0,r0 - 100020: 4e 80 00 20 blr +0000000000100028 : + 100028: 7c 6a 59 10 subfe r3,r10,r11 + 10002c: 7c 80 01 14 adde r4,r0,r0 + 100030: 4e 80 00 20 blr -0000000000100024 : - 100024: 7c 6a 59 10 subfe r3,r10,r11 - 100028: 7c 80 01 14 adde r4,r0,r0 - 10002c: 4e 80 00 20 blr +0000000000100034 : + 100034: 39 40 00 00 li r10,0 + 100038: 39 60 00 00 li r11,0 + 10003c: 7c 6a 59 10 subfe r3,r10,r11 + 100040: 7c 80 01 14 adde r4,r0,r0 + 100044: 4e 80 00 20 blr -0000000000100030 : - 100030: 7c 6a 59 10 subfe r3,r10,r11 - 100034: 7c 80 01 14 adde r4,r0,r0 - 100038: 4e 80 00 20 blr +0000000000100048 : + 100048: 7c 6a 59 10 subfe r3,r10,r11 + 10004c: 7c 80 01 14 adde r4,r0,r0 + 100050: 4e 80 00 20 blr + +0000000000100054 : + 100054: 39 40 00 01 li r10,1 + 100058: 39 60 00 00 li r11,0 + 10005c: 7c 6a 59 10 subfe r3,r10,r11 + 100060: 7c 80 01 14 adde r4,r0,r0 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 7c 6a 59 10 subfe r3,r10,r11 + 10006c: 7c 80 01 14 adde r4,r0,r0 + 100070: 4e 80 00 20 blr + +0000000000100074 : + 100074: 39 40 00 00 li r10,0 + 100078: 39 60 00 01 li r11,1 + 10007c: 7c 6a 59 10 subfe r3,r10,r11 + 100080: 7c 80 01 14 adde r4,r0,r0 + 100084: 4e 80 00 20 blr + +0000000000100088 : + 100088: 7c 6a 59 10 subfe r3,r10,r11 + 10008c: 7c 80 01 14 adde r4,r0,r0 + 100090: 4e 80 00 20 blr + +0000000000100094 : + 100094: 39 40 ff ff li r10,-1 + 100098: 39 60 ff ff li r11,-1 + 10009c: 7c 6a 59 10 subfe r3,r10,r11 + 1000a0: 7c 80 01 14 adde r4,r0,r0 + 1000a4: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_subfe.map b/src/xenia/cpu/frontend/test/bin/instr_subfe.map index 841bd25db..8db082139 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_subfe.map +++ b/src/xenia/cpu/frontend/test/bin/instr_subfe.map @@ -1,5 +1,10 @@ 0000000000000000 t test_subfe_1 -000000000000000c t test_subfe_2 -0000000000000018 t test_subfe_3 -0000000000000024 t test_subfe_4 -0000000000000030 t test_subfe_5 +000000000000000c t test_subfe_1_constant +0000000000000028 t test_subfe_2 +0000000000000034 t test_subfe_2_constant +0000000000000048 t test_subfe_3 +0000000000000054 t test_subfe_3_constant +0000000000000068 t test_subfe_4 +0000000000000074 t test_subfe_4_constant +0000000000000088 t test_subfe_5 +0000000000000094 t test_subfe_5_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_subfic.bin b/src/xenia/cpu/frontend/test/bin/instr_subfic.bin index a46c4507d1257836b3a4ef8d28857fc67a88acec..8ed89eff8399e20b26652557b3ecc4275c17635d 100644 GIT binary patch literal 176 zcmY$$Vm?sQz$oI^z@T93z`&U3#k^kuNlYQ@zZj-GLQElxfdM9O>A=8%%tvMe: - 10000c: 20 6a ff 16 subfic r3,r10,-234 - 100010: 7c 80 01 14 adde r4,r0,r0 - 100014: 4e 80 00 20 blr +000000000010000c : + 10000c: 3d 40 00 01 lis r10,1 + 100010: 61 4a 03 bf ori r10,r10,959 + 100014: 20 6a 03 c0 subfic r3,r10,960 + 100018: 7c 80 01 14 adde r4,r0,r0 + 10001c: 4e 80 00 20 blr -0000000000100018 : - 100018: 20 6a 00 00 subfic r3,r10,0 - 10001c: 7c 80 01 14 adde r4,r0,r0 - 100020: 4e 80 00 20 blr +0000000000100020 : + 100020: 20 6a ff 16 subfic r3,r10,-234 + 100024: 7c 80 01 14 adde r4,r0,r0 + 100028: 4e 80 00 20 blr -0000000000100024 : - 100024: 20 6a 00 00 subfic r3,r10,0 - 100028: 7c 80 01 14 adde r4,r0,r0 - 10002c: 4e 80 00 20 blr +000000000010002c : + 10002c: 3d 40 00 01 lis r10,1 + 100030: 61 4a 03 bf ori r10,r10,959 + 100034: 20 6a ff 16 subfic r3,r10,-234 + 100038: 7c 80 01 14 adde r4,r0,r0 + 10003c: 4e 80 00 20 blr -0000000000100030 : - 100030: 20 6a 00 01 subfic r3,r10,1 - 100034: 7c 80 01 14 adde r4,r0,r0 - 100038: 4e 80 00 20 blr +0000000000100040 : + 100040: 20 6a 00 00 subfic r3,r10,0 + 100044: 7c 80 01 14 adde r4,r0,r0 + 100048: 4e 80 00 20 blr -000000000010003c : - 10003c: 20 6a ff ff subfic r3,r10,-1 - 100040: 7c 80 01 14 adde r4,r0,r0 - 100044: 4e 80 00 20 blr +000000000010004c : + 10004c: 39 40 00 00 li r10,0 + 100050: 20 6a 00 00 subfic r3,r10,0 + 100054: 7c 80 01 14 adde r4,r0,r0 + 100058: 4e 80 00 20 blr + +000000000010005c : + 10005c: 20 6a 00 00 subfic r3,r10,0 + 100060: 7c 80 01 14 adde r4,r0,r0 + 100064: 4e 80 00 20 blr + +0000000000100068 : + 100068: 39 40 00 01 li r10,1 + 10006c: 20 6a 00 00 subfic r3,r10,0 + 100070: 7c 80 01 14 adde r4,r0,r0 + 100074: 4e 80 00 20 blr + +0000000000100078 : + 100078: 20 6a 00 01 subfic r3,r10,1 + 10007c: 7c 80 01 14 adde r4,r0,r0 + 100080: 4e 80 00 20 blr + +0000000000100084 : + 100084: 39 40 00 00 li r10,0 + 100088: 20 6a 00 01 subfic r3,r10,1 + 10008c: 7c 80 01 14 adde r4,r0,r0 + 100090: 4e 80 00 20 blr + +0000000000100094 : + 100094: 20 6a ff ff subfic r3,r10,-1 + 100098: 7c 80 01 14 adde r4,r0,r0 + 10009c: 4e 80 00 20 blr + +00000000001000a0 : + 1000a0: 39 40 ff ff li r10,-1 + 1000a4: 20 6a ff ff subfic r3,r10,-1 + 1000a8: 7c 80 01 14 adde r4,r0,r0 + 1000ac: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_subfic.map b/src/xenia/cpu/frontend/test/bin/instr_subfic.map index 6c4f55f29..eb28d3c76 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_subfic.map +++ b/src/xenia/cpu/frontend/test/bin/instr_subfic.map @@ -1,6 +1,12 @@ 0000000000000000 t test_subfic_1 -000000000000000c t test_subfic_2 -0000000000000018 t test_subfic_3 -0000000000000024 t test_subfic_4 -0000000000000030 t test_subfic_5 -000000000000003c t test_subfic_6 +000000000000000c t test_subfic_1_constant +0000000000000020 t test_subfic_2 +000000000000002c t test_subfic_2_constant +0000000000000040 t test_subfic_3 +000000000000004c t test_subfic_3_constant +000000000000005c t test_subfic_4 +0000000000000068 t test_subfic_4_constant +0000000000000078 t test_subfic_5 +0000000000000084 t test_subfic_5_constant +0000000000000094 t test_subfic_6 +00000000000000a0 t test_subfic_6_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_subfme.bin b/src/xenia/cpu/frontend/test/bin/instr_subfme.bin index c27f4a204aab9c1bd3a7446a6d3873d808526e23..68c8fd7daf4e463e2546efc002a2e0699bd19f3c 100644 GIT binary patch literal 392 zcmbpmiS?i%)nTa#dx8nflG1zQE;*1mKL4Q0VN(zD2a#&Q?k7$y#NFs>0UAVg(*OVf delta 29 YcmeBR-oQ9f!C>M72_Twmz$k)@0gDv~5C8xG diff --git a/src/xenia/cpu/frontend/test/bin/instr_subfme.dis b/src/xenia/cpu/frontend/test/bin/instr_subfme.dis index 5ae1f889e..b7bd8f9d0 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_subfme.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_subfme.dis @@ -8,54 +8,124 @@ Disassembly of section .text: 100010: 7c 80 01 14 adde r4,r0,r0 100014: 4e 80 00 20 blr -0000000000100018 : - 100018: 7c 63 1a 78 xor r3,r3,r3 - 10001c: 7c 63 18 f8 not r3,r3 - 100020: 30 63 00 01 addic r3,r3,1 - 100024: 7c 6a 01 d0 subfme r3,r10 - 100028: 7c 80 01 14 adde r4,r0,r0 - 10002c: 4e 80 00 20 blr +0000000000100018 : + 100018: 3d 40 00 01 lis r10,1 + 10001c: 61 4a 03 bf ori r10,r10,959 + 100020: 7c 63 1a 78 xor r3,r3,r3 + 100024: 7c 63 18 f8 not r3,r3 + 100028: 30 63 00 01 addic r3,r3,1 + 10002c: 7c 6a 01 d0 subfme r3,r10 + 100030: 7c 80 01 14 adde r4,r0,r0 + 100034: 4e 80 00 20 blr -0000000000100030 : - 100030: 7c 63 1a 78 xor r3,r3,r3 - 100034: 7c 63 18 f8 not r3,r3 - 100038: 30 63 00 01 addic r3,r3,1 - 10003c: 7c 6a 01 d0 subfme r3,r10 - 100040: 7c 80 01 14 adde r4,r0,r0 - 100044: 4e 80 00 20 blr +0000000000100038 : + 100038: 7c 63 1a 78 xor r3,r3,r3 + 10003c: 7c 63 18 f8 not r3,r3 + 100040: 30 63 00 01 addic r3,r3,1 + 100044: 7c 6a 01 d0 subfme r3,r10 + 100048: 7c 80 01 14 adde r4,r0,r0 + 10004c: 4e 80 00 20 blr -0000000000100048 : - 100048: 7c 63 1a 78 xor r3,r3,r3 - 10004c: 7c 63 18 f8 not r3,r3 - 100050: 30 63 00 01 addic r3,r3,1 - 100054: 7c 6a 01 d0 subfme r3,r10 - 100058: 7c 80 01 14 adde r4,r0,r0 - 10005c: 4e 80 00 20 blr +0000000000100050 : + 100050: 39 40 00 00 li r10,0 + 100054: 7c 63 1a 78 xor r3,r3,r3 + 100058: 7c 63 18 f8 not r3,r3 + 10005c: 30 63 00 01 addic r3,r3,1 + 100060: 7c 6a 01 d0 subfme r3,r10 + 100064: 7c 80 01 14 adde r4,r0,r0 + 100068: 4e 80 00 20 blr -0000000000100060 : - 100060: 7c 63 1a 78 xor r3,r3,r3 - 100064: 30 63 00 01 addic r3,r3,1 - 100068: 7c 6a 01 d0 subfme r3,r10 - 10006c: 7c 80 01 14 adde r4,r0,r0 - 100070: 4e 80 00 20 blr +000000000010006c : + 10006c: 7c 63 1a 78 xor r3,r3,r3 + 100070: 7c 63 18 f8 not r3,r3 + 100074: 30 63 00 01 addic r3,r3,1 + 100078: 7c 6a 01 d0 subfme r3,r10 + 10007c: 7c 80 01 14 adde r4,r0,r0 + 100080: 4e 80 00 20 blr -0000000000100074 : - 100074: 7c 63 1a 78 xor r3,r3,r3 - 100078: 30 63 00 01 addic r3,r3,1 - 10007c: 7c 6a 01 d0 subfme r3,r10 - 100080: 7c 80 01 14 adde r4,r0,r0 - 100084: 4e 80 00 20 blr - -0000000000100088 : +0000000000100084 : + 100084: 39 40 00 01 li r10,1 100088: 7c 63 1a 78 xor r3,r3,r3 - 10008c: 30 63 00 01 addic r3,r3,1 - 100090: 7c 6a 01 d0 subfme r3,r10 - 100094: 7c 80 01 14 adde r4,r0,r0 - 100098: 4e 80 00 20 blr + 10008c: 7c 63 18 f8 not r3,r3 + 100090: 30 63 00 01 addic r3,r3,1 + 100094: 7c 6a 01 d0 subfme r3,r10 + 100098: 7c 80 01 14 adde r4,r0,r0 + 10009c: 4e 80 00 20 blr -000000000010009c : - 10009c: 7c 63 1a 78 xor r3,r3,r3 - 1000a0: 30 63 00 01 addic r3,r3,1 - 1000a4: 7c 6a 01 d0 subfme r3,r10 - 1000a8: 7c 80 01 14 adde r4,r0,r0 - 1000ac: 4e 80 00 20 blr +00000000001000a0 : + 1000a0: 7c 63 1a 78 xor r3,r3,r3 + 1000a4: 7c 63 18 f8 not r3,r3 + 1000a8: 30 63 00 01 addic r3,r3,1 + 1000ac: 7c 6a 01 d0 subfme r3,r10 + 1000b0: 7c 80 01 14 adde r4,r0,r0 + 1000b4: 4e 80 00 20 blr + +00000000001000b8 : + 1000b8: 39 40 ff ff li r10,-1 + 1000bc: 7c 63 1a 78 xor r3,r3,r3 + 1000c0: 7c 63 18 f8 not r3,r3 + 1000c4: 30 63 00 01 addic r3,r3,1 + 1000c8: 7c 6a 01 d0 subfme r3,r10 + 1000cc: 7c 80 01 14 adde r4,r0,r0 + 1000d0: 4e 80 00 20 blr + +00000000001000d4 : + 1000d4: 7c 63 1a 78 xor r3,r3,r3 + 1000d8: 30 63 00 01 addic r3,r3,1 + 1000dc: 7c 6a 01 d0 subfme r3,r10 + 1000e0: 7c 80 01 14 adde r4,r0,r0 + 1000e4: 4e 80 00 20 blr + +00000000001000e8 : + 1000e8: 3d 40 00 01 lis r10,1 + 1000ec: 61 4a 03 bf ori r10,r10,959 + 1000f0: 7c 63 1a 78 xor r3,r3,r3 + 1000f4: 30 63 00 01 addic r3,r3,1 + 1000f8: 7c 6a 01 d0 subfme r3,r10 + 1000fc: 7c 80 01 14 adde r4,r0,r0 + 100100: 4e 80 00 20 blr + +0000000000100104 : + 100104: 7c 63 1a 78 xor r3,r3,r3 + 100108: 30 63 00 01 addic r3,r3,1 + 10010c: 7c 6a 01 d0 subfme r3,r10 + 100110: 7c 80 01 14 adde r4,r0,r0 + 100114: 4e 80 00 20 blr + +0000000000100118 : + 100118: 39 40 00 00 li r10,0 + 10011c: 7c 63 1a 78 xor r3,r3,r3 + 100120: 30 63 00 01 addic r3,r3,1 + 100124: 7c 6a 01 d0 subfme r3,r10 + 100128: 7c 80 01 14 adde r4,r0,r0 + 10012c: 4e 80 00 20 blr + +0000000000100130 : + 100130: 7c 63 1a 78 xor r3,r3,r3 + 100134: 30 63 00 01 addic r3,r3,1 + 100138: 7c 6a 01 d0 subfme r3,r10 + 10013c: 7c 80 01 14 adde r4,r0,r0 + 100140: 4e 80 00 20 blr + +0000000000100144 : + 100144: 39 40 00 01 li r10,1 + 100148: 7c 63 1a 78 xor r3,r3,r3 + 10014c: 30 63 00 01 addic r3,r3,1 + 100150: 7c 6a 01 d0 subfme r3,r10 + 100154: 7c 80 01 14 adde r4,r0,r0 + 100158: 4e 80 00 20 blr + +000000000010015c : + 10015c: 7c 63 1a 78 xor r3,r3,r3 + 100160: 30 63 00 01 addic r3,r3,1 + 100164: 7c 6a 01 d0 subfme r3,r10 + 100168: 7c 80 01 14 adde r4,r0,r0 + 10016c: 4e 80 00 20 blr + +0000000000100170 : + 100170: 39 40 ff ff li r10,-1 + 100174: 7c 63 1a 78 xor r3,r3,r3 + 100178: 30 63 00 01 addic r3,r3,1 + 10017c: 7c 6a 01 d0 subfme r3,r10 + 100180: 7c 80 01 14 adde r4,r0,r0 + 100184: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_subfme.map b/src/xenia/cpu/frontend/test/bin/instr_subfme.map index f687dd0f8..dae69ad57 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_subfme.map +++ b/src/xenia/cpu/frontend/test/bin/instr_subfme.map @@ -1,8 +1,16 @@ 0000000000000000 t test_subfme_one_ca_1 -0000000000000018 t test_subfme_one_ca_2 -0000000000000030 t test_subfme_one_ca_3 -0000000000000048 t test_subfme_one_ca_4 -0000000000000060 t test_subfme_zero_ca_1 -0000000000000074 t test_subfme_zero_ca_2 -0000000000000088 t test_subfme_zero_ca_3 -000000000000009c t test_subfme_zero_ca_4 +0000000000000018 t test_subfme_one_ca_1_constant +0000000000000038 t test_subfme_one_ca_2 +0000000000000050 t test_subfme_one_ca_2_constant +000000000000006c t test_subfme_one_ca_3 +0000000000000084 t test_subfme_one_ca_3_constant +00000000000000a0 t test_subfme_one_ca_4 +00000000000000b8 t test_subfme_one_ca_4_constant +00000000000000d4 t test_subfme_zero_ca_1 +00000000000000e8 t test_subfme_zero_ca_1_constant +0000000000000104 t test_subfme_zero_ca_2 +0000000000000118 t test_subfme_zero_ca_2_constant +0000000000000130 t test_subfme_zero_ca_3 +0000000000000144 t test_subfme_zero_ca_3_constant +000000000000015c t test_subfme_zero_ca_4 +0000000000000170 t test_subfme_zero_ca_4_constant diff --git a/src/xenia/cpu/frontend/test/bin/instr_subfze.bin b/src/xenia/cpu/frontend/test/bin/instr_subfze.bin index 4f1ba543b7608bdb96a2e1c767599ef6259e4bb4..ba4a59fa7e5b67908a4084fefdac62f071a63509 100644 GIT binary patch literal 392 zcmbpmiS?i%)nTa#WG1zQE;*1mKL4Q0VN(zD2a#&Q?k7$y#NFs>0XP?N(*OVf delta 29 YcmeBR-oQ9f!C>M72_Twmz$k)@0gDv~5C8xG diff --git a/src/xenia/cpu/frontend/test/bin/instr_subfze.dis b/src/xenia/cpu/frontend/test/bin/instr_subfze.dis index c38bbc820..66a313a1b 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_subfze.dis +++ b/src/xenia/cpu/frontend/test/bin/instr_subfze.dis @@ -8,54 +8,124 @@ Disassembly of section .text: 100010: 7c 80 01 14 adde r4,r0,r0 100014: 4e 80 00 20 blr -0000000000100018 : - 100018: 7c 63 1a 78 xor r3,r3,r3 - 10001c: 7c 63 18 f8 not r3,r3 - 100020: 30 63 00 01 addic r3,r3,1 - 100024: 7c 6a 01 90 subfze r3,r10 - 100028: 7c 80 01 14 adde r4,r0,r0 - 10002c: 4e 80 00 20 blr +0000000000100018 : + 100018: 3d 40 00 01 lis r10,1 + 10001c: 61 4a 03 bf ori r10,r10,959 + 100020: 7c 63 1a 78 xor r3,r3,r3 + 100024: 7c 63 18 f8 not r3,r3 + 100028: 30 63 00 01 addic r3,r3,1 + 10002c: 7c 6a 01 90 subfze r3,r10 + 100030: 7c 80 01 14 adde r4,r0,r0 + 100034: 4e 80 00 20 blr -0000000000100030 : - 100030: 7c 63 1a 78 xor r3,r3,r3 - 100034: 7c 63 18 f8 not r3,r3 - 100038: 30 63 00 01 addic r3,r3,1 - 10003c: 7c 6a 01 90 subfze r3,r10 - 100040: 7c 80 01 14 adde r4,r0,r0 - 100044: 4e 80 00 20 blr +0000000000100038 : + 100038: 7c 63 1a 78 xor r3,r3,r3 + 10003c: 7c 63 18 f8 not r3,r3 + 100040: 30 63 00 01 addic r3,r3,1 + 100044: 7c 6a 01 90 subfze r3,r10 + 100048: 7c 80 01 14 adde r4,r0,r0 + 10004c: 4e 80 00 20 blr -0000000000100048 : - 100048: 7c 63 1a 78 xor r3,r3,r3 - 10004c: 7c 63 18 f8 not r3,r3 - 100050: 30 63 00 01 addic r3,r3,1 - 100054: 7c 6a 01 90 subfze r3,r10 - 100058: 7c 80 01 14 adde r4,r0,r0 - 10005c: 4e 80 00 20 blr +0000000000100050 : + 100050: 39 40 00 00 li r10,0 + 100054: 7c 63 1a 78 xor r3,r3,r3 + 100058: 7c 63 18 f8 not r3,r3 + 10005c: 30 63 00 01 addic r3,r3,1 + 100060: 7c 6a 01 90 subfze r3,r10 + 100064: 7c 80 01 14 adde r4,r0,r0 + 100068: 4e 80 00 20 blr -0000000000100060 : - 100060: 7c 63 1a 78 xor r3,r3,r3 - 100064: 30 63 00 01 addic r3,r3,1 - 100068: 7c 6a 01 90 subfze r3,r10 - 10006c: 7c 80 01 14 adde r4,r0,r0 - 100070: 4e 80 00 20 blr +000000000010006c : + 10006c: 7c 63 1a 78 xor r3,r3,r3 + 100070: 7c 63 18 f8 not r3,r3 + 100074: 30 63 00 01 addic r3,r3,1 + 100078: 7c 6a 01 90 subfze r3,r10 + 10007c: 7c 80 01 14 adde r4,r0,r0 + 100080: 4e 80 00 20 blr -0000000000100074 : - 100074: 7c 63 1a 78 xor r3,r3,r3 - 100078: 30 63 00 01 addic r3,r3,1 - 10007c: 7c 6a 01 90 subfze r3,r10 - 100080: 7c 80 01 14 adde r4,r0,r0 - 100084: 4e 80 00 20 blr - -0000000000100088 : +0000000000100084 : + 100084: 39 40 00 01 li r10,1 100088: 7c 63 1a 78 xor r3,r3,r3 - 10008c: 30 63 00 01 addic r3,r3,1 - 100090: 7c 6a 01 90 subfze r3,r10 - 100094: 7c 80 01 14 adde r4,r0,r0 - 100098: 4e 80 00 20 blr + 10008c: 7c 63 18 f8 not r3,r3 + 100090: 30 63 00 01 addic r3,r3,1 + 100094: 7c 6a 01 90 subfze r3,r10 + 100098: 7c 80 01 14 adde r4,r0,r0 + 10009c: 4e 80 00 20 blr -000000000010009c : - 10009c: 7c 63 1a 78 xor r3,r3,r3 - 1000a0: 30 63 00 01 addic r3,r3,1 - 1000a4: 7c 6a 01 90 subfze r3,r10 - 1000a8: 7c 80 01 14 adde r4,r0,r0 - 1000ac: 4e 80 00 20 blr +00000000001000a0 : + 1000a0: 7c 63 1a 78 xor r3,r3,r3 + 1000a4: 7c 63 18 f8 not r3,r3 + 1000a8: 30 63 00 01 addic r3,r3,1 + 1000ac: 7c 6a 01 90 subfze r3,r10 + 1000b0: 7c 80 01 14 adde r4,r0,r0 + 1000b4: 4e 80 00 20 blr + +00000000001000b8 : + 1000b8: 39 40 ff ff li r10,-1 + 1000bc: 7c 63 1a 78 xor r3,r3,r3 + 1000c0: 7c 63 18 f8 not r3,r3 + 1000c4: 30 63 00 01 addic r3,r3,1 + 1000c8: 7c 6a 01 90 subfze r3,r10 + 1000cc: 7c 80 01 14 adde r4,r0,r0 + 1000d0: 4e 80 00 20 blr + +00000000001000d4 : + 1000d4: 7c 63 1a 78 xor r3,r3,r3 + 1000d8: 30 63 00 01 addic r3,r3,1 + 1000dc: 7c 6a 01 90 subfze r3,r10 + 1000e0: 7c 80 01 14 adde r4,r0,r0 + 1000e4: 4e 80 00 20 blr + +00000000001000e8 : + 1000e8: 3d 40 00 01 lis r10,1 + 1000ec: 61 4a 03 bf ori r10,r10,959 + 1000f0: 7c 63 1a 78 xor r3,r3,r3 + 1000f4: 30 63 00 01 addic r3,r3,1 + 1000f8: 7c 6a 01 90 subfze r3,r10 + 1000fc: 7c 80 01 14 adde r4,r0,r0 + 100100: 4e 80 00 20 blr + +0000000000100104 : + 100104: 7c 63 1a 78 xor r3,r3,r3 + 100108: 30 63 00 01 addic r3,r3,1 + 10010c: 7c 6a 01 90 subfze r3,r10 + 100110: 7c 80 01 14 adde r4,r0,r0 + 100114: 4e 80 00 20 blr + +0000000000100118 : + 100118: 39 40 00 00 li r10,0 + 10011c: 7c 63 1a 78 xor r3,r3,r3 + 100120: 30 63 00 01 addic r3,r3,1 + 100124: 7c 6a 01 90 subfze r3,r10 + 100128: 7c 80 01 14 adde r4,r0,r0 + 10012c: 4e 80 00 20 blr + +0000000000100130 : + 100130: 7c 63 1a 78 xor r3,r3,r3 + 100134: 30 63 00 01 addic r3,r3,1 + 100138: 7c 6a 01 90 subfze r3,r10 + 10013c: 7c 80 01 14 adde r4,r0,r0 + 100140: 4e 80 00 20 blr + +0000000000100144 : + 100144: 39 40 00 01 li r10,1 + 100148: 7c 63 1a 78 xor r3,r3,r3 + 10014c: 30 63 00 01 addic r3,r3,1 + 100150: 7c 6a 01 90 subfze r3,r10 + 100154: 7c 80 01 14 adde r4,r0,r0 + 100158: 4e 80 00 20 blr + +000000000010015c : + 10015c: 7c 63 1a 78 xor r3,r3,r3 + 100160: 30 63 00 01 addic r3,r3,1 + 100164: 7c 6a 01 90 subfze r3,r10 + 100168: 7c 80 01 14 adde r4,r0,r0 + 10016c: 4e 80 00 20 blr + +0000000000100170 : + 100170: 39 40 ff ff li r10,-1 + 100174: 7c 63 1a 78 xor r3,r3,r3 + 100178: 30 63 00 01 addic r3,r3,1 + 10017c: 7c 6a 01 90 subfze r3,r10 + 100180: 7c 80 01 14 adde r4,r0,r0 + 100184: 4e 80 00 20 blr diff --git a/src/xenia/cpu/frontend/test/bin/instr_subfze.map b/src/xenia/cpu/frontend/test/bin/instr_subfze.map index b161c026a..fc3d7fe2b 100644 --- a/src/xenia/cpu/frontend/test/bin/instr_subfze.map +++ b/src/xenia/cpu/frontend/test/bin/instr_subfze.map @@ -1,8 +1,16 @@ 0000000000000000 t test_subfze_one_ca_1 -0000000000000018 t test_subfze_one_ca_2 -0000000000000030 t test_subfze_one_ca_3 -0000000000000048 t test_subfze_one_ca_4 -0000000000000060 t test_subfze_zero_ca_1 -0000000000000074 t test_subfze_zero_ca_2 -0000000000000088 t test_subfze_zero_ca_3 -000000000000009c t test_subfze_zero_ca_4 +0000000000000018 t test_subfze_one_ca_1_constant +0000000000000038 t test_subfze_one_ca_2 +0000000000000050 t test_subfze_one_ca_2_constant +000000000000006c t test_subfze_one_ca_3 +0000000000000084 t test_subfze_one_ca_3_constant +00000000000000a0 t test_subfze_one_ca_4 +00000000000000b8 t test_subfze_one_ca_4_constant +00000000000000d4 t test_subfze_zero_ca_1 +00000000000000e8 t test_subfze_zero_ca_1_constant +0000000000000104 t test_subfze_zero_ca_2 +0000000000000118 t test_subfze_zero_ca_2_constant +0000000000000130 t test_subfze_zero_ca_3 +0000000000000144 t test_subfze_zero_ca_3_constant +000000000000015c t test_subfze_zero_ca_4 +0000000000000170 t test_subfze_zero_ca_4_constant diff --git a/src/xenia/cpu/hir/value.cc b/src/xenia/cpu/hir/value.cc index 89e3a2f4a..f674cabee 100644 --- a/src/xenia/cpu/hir/value.cc +++ b/src/xenia/cpu/hir/value.cc @@ -244,24 +244,28 @@ bool Value::Add(Value* other) { } bool Value::Sub(Value* other) { -#define SUB_DID_CARRY(a, b) (b > a) +#define SUB_DID_CARRY(a, b) (b == 0 || a > (~(0-b))) assert_true(type == other->type); bool did_carry = false; switch (type) { case INT8_TYPE: - did_carry = SUB_DID_CARRY(constant.i8, other->constant.i8); + did_carry = + SUB_DID_CARRY(uint16_t(constant.i8), uint16_t(other->constant.i8)); constant.i8 -= other->constant.i8; break; case INT16_TYPE: - did_carry = SUB_DID_CARRY(constant.i16, other->constant.i16); + did_carry = + SUB_DID_CARRY(uint16_t(constant.i16), uint16_t(other->constant.i16)); constant.i16 -= other->constant.i16; break; case INT32_TYPE: - did_carry = SUB_DID_CARRY(constant.i32, other->constant.i32); + did_carry = + SUB_DID_CARRY(uint32_t(constant.i32), uint32_t(other->constant.i32)); constant.i32 -= other->constant.i32; break; case INT64_TYPE: - did_carry = SUB_DID_CARRY(constant.i64, other->constant.i64); + did_carry = + SUB_DID_CARRY(uint64_t(constant.i64), uint64_t(other->constant.i64)); constant.i64 -= other->constant.i64; break; case FLOAT32_TYPE: