# vpkd3d128 dest, src, type, mask, shift
# type:
#   0 = PACK_TYPE_D3DCOLOR
#   1 = PACK_TYPE_SHORT_2
#   2 = PACK_TYPE_2_10_10_10
#   3 = PACK_TYPE_FLOAT16_2
#   4 = PACK_TYPE_SHORT_4
#   5 = PACK_TYPE_FLOAT16_4
# mask:
#   must not be zero
#   1 = 00000000 00000000 00000000 FFFFFFFF
#   2 = 00000000 00000000 FFFFFFFF FFFFFFFF
#   3 = same as 2? except mask3/shift3
# shift:
#   0 = no shift
#   1 = shift left by one word
#   2 ...
#   3 ...
# special case: mask3/shift3 = 00000000 00000000 00000000 FFFFFFFF

# vpkd3d128 is broken in binutils, so these are hand coded

test_vpkd3d128_d3dcolor_invalid_0:
  #_ REGISTER_IN v3 [00000001, 00000002, 00000003, 00000004]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 0, 1, 0
  .long 0x18811E10
  blr
  #_ REGISTER_OUT v3 [00000001, 00000002, 00000003, 00000004]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000]
test_vpkd3d128_d3dcolor_invalid_1:
  #_ REGISTER_IN v3 [40800000, 40000000, C2F60000, 4B3BDF83]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 0, 1, 0
  .long 0x18811E10
  blr
  #_ REGISTER_OUT v3 [40800000, 40000000, C2F60000, 4B3BDF83]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, FFFF0000]
test_vpkd3d128_d3dcolor_invalid_2:
  #_ REGISTER_IN v3 [40800000, 40000000, C2F60000, FFFFFFFF]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 0, 1, 0
  .long 0x18811E10
  blr
  #_ REGISTER_OUT v3 [40800000, 40000000, C2F60000, FFFFFFFF]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00FF0000]

test_vpkd3d128_d3dcolor_1_0:
  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 0, 1, 0
  .long 0x18811E10
  blr
  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 04010203]
test_vpkd3d128_d3dcolor_1_1:
  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 0, 1, 1
  .long 0x18811E50
  blr
  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 04010203, CDCDCDCD]
test_vpkd3d128_d3dcolor_1_2:
  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 0, 1, 2
  .long 0x18811E90
  blr
  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_OUT v4 [CDCDCDCD, 04010203, CDCDCDCD, CDCDCDCD]
test_vpkd3d128_d3dcolor_1_3:
  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 0, 1, 3
  .long 0x18811ED0
  blr
  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_OUT v4 [04010203, CDCDCDCD, CDCDCDCD, CDCDCDCD]

test_vpkd3d128_d3dcolor_2_0:
  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 0, 2, 0
  .long 0x18821E10
  blr
  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 00000000, 04010203]
test_vpkd3d128_d3dcolor_2_1:
  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 0, 2, 1
  .long 0x18821E50
  blr
  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_OUT v4 [CDCDCDCD, 00000000, 04010203, CDCDCDCD]
test_vpkd3d128_d3dcolor_2_2:
  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 0, 2, 2
  .long 0x18821E90
  blr
  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_OUT v4 [00000000, 04010203, CDCDCDCD, CDCDCDCD]
test_vpkd3d128_d3dcolor_2_3:
  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 0, 2, 3
  .long 0x18821ED0
  blr
  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_OUT v4 [04010203, CDCDCDCD, CDCDCDCD, CDCDCDCD]

test_vpkd3d128_d3dcolor_3_0:
  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 0, 3, 0
  .long 0x18831E10
  blr
  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 00000000, 04010203]
test_vpkd3d128_d3dcolor_3_1:
  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 0, 3, 1
  .long 0x18831E50
  blr
  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_OUT v4 [CDCDCDCD, 00000000, 04010203, CDCDCDCD]
test_vpkd3d128_d3dcolor_3_2:
  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 0, 3, 2
  .long 0x18831E90
  blr
  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_OUT v4 [00000000, 04010203, CDCDCDCD, CDCDCDCD]
test_vpkd3d128_d3dcolor_3_3:
  #_ REGISTER_IN v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 0, 3, 3
  .long 0x18831ED0
  blr
  #_ REGISTER_OUT v3 [40400001, 40400002, 40400003, 40400004]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 00000000]


test_vpkd3d128_short2_invalid_0:
  #_ REGISTER_IN v3 [43817E00, C37CFC00, 42A23EC8, 403DB757]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 1, 1, 0
  .long 0x18851E10
  blr
  #_ REGISTER_OUT v3 [43817E00, C37CFC00, 42A23EC8, 403DB757]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001]
test_vpkd3d128_short2_invalid_1:
  #_ REGISTER_IN v3 [412FDF00, C09FBE00, 42A23EC8, 403DB757]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 1, 1, 0
  .long 0x18851E10
  blr
  #_ REGISTER_OUT v3 [412FDF00, C09FBE00, 42A23EC8, 403DB757]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001]

test_vpkd3d128_short2_0:
  #_ REGISTER_IN v3 [40407FFF, 403F8001, 00000000, 00000000]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 1, 1, 0
  .long 0x18851E10
  blr
  #_ REGISTER_OUT v3 [40407FFF, 403F8001, 00000000, 00000000]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFF8001]
test_vpkd3d128_short2_1:
  #_ REGISTER_IN v3 [40404000, 403FC000, 40400003, 403F8001]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 1, 1, 0
  .long 0x18851E10
  blr
  #_ REGISTER_OUT v3 [40404000, 403FC000, 40400003, 403F8001]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 4000C000]
test_vpkd3d128_short2_2:
  #_ REGISTER_IN v3 [4040FFFE, 403FF333, 42A23EC8, 403DB757]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 1, 1, 0
  .long 0x18851E10
  blr
  #_ REGISTER_OUT v3 [4040FFFE, 403FF333, 42A23EC8, 403DB757]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 7FFFF333]

test_vpkd3d128_short4_0:
  # v3 = [1.5, -1.5, 1.5, -1.5]
  #_ REGISTER_IN v3 [403F8001, 403FFFF8, 4040007F, 40400000]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 4, 2, 0
  .long 0x18921E10
  blr
  #_ REGISTER_OUT v3 [403F8001, 403FFFF8, 4040007F, 40400000]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 8001FFF8, 007F0000]

test_vpkd3d128_uint_2101010_0:
  #_ REGISTER_IN v3 [B8FF8000, B8FF8000, C04001FF, 4E9A5A5A]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 2, 1, 0
  .long 0x18891E10
  blr
  #_ REGISTER_OUT v3 [B8FF8000, B8FF8000, C04001FF, 4E9A5A5A]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, E0180601]
test_vpkd3d128_uint_2101010_1:
  #_ REGISTER_IN v3 [42C80000, C2C80000, 40400000, 3F800000]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 2, 1, 0
  .long 0x18891E10
  blr
  #_ REGISTER_OUT v3 [42C80000, C2C80000, 40400000, 3F800000]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 000805FF]
test_vpkd3d128_uint_2101010_2:
  #_ REGISTER_IN v3 [3F000000, BF000000, 3F800000, 00000000]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 2, 1, 0
  .long 0x18891E10
  blr
  #_ REGISTER_OUT v3 [3F000000, BF000000, 3F800000, 00000000]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 20180601]


test_vpkd3d128_float16_2_invalid_0:
  #_ REGISTER_IN v3 [3FC00000, BFC00000, 42A23EC8, 403DB757]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 3, 1, 0
  .long 0x188D1E10
  blr
  #_ REGISTER_OUT v3 [3FC00000, BFC00000, 42A23EC8, 403DB757]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 3E00BE00]
test_vpkd3d128_float16_2_0:
  #_ REGISTER_IN v3 [3F000000, BF000000, 00000000, 00000000]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 3, 1, 0
  .long 0x188D1E10
  blr
  #_ REGISTER_OUT v3 [3F000000, BF000000, 00000000, 00000000]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, 3800B800]

test_vpkd3d128_float16_4_invalid_0:
  #_ REGISTER_IN v3 [3FC00000, BFC00000, 3FC00000, BFC00000]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 5, 2, 0
  .long 0x18961E10
  blr
  #_ REGISTER_OUT v3 [3FC00000, BFC00000, 3FC00000, BFC00000]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 3E00BE00, 3E00BE00]
test_vpkd3d128_float16_4_0:
  #_ REGISTER_IN v3 [3F000000, BF000000, 3F800000, BF800000]
  #_ REGISTER_IN v4 [CDCDCDCD, CDCDCDCD, CDCDCDCD, CDCDCDCD]
  # vpkd3d128 v4, v3, 5, 2, 0
  .long 0x18961E10
  blr
  #_ REGISTER_OUT v3 [3F000000, BF000000, 3F800000, BF800000]
  #_ REGISTER_OUT v4 [CDCDCDCD, CDCDCDCD, 3800B800, 3C00BC00]
