//
// Generated by Microsoft (R) HLSL Shader Compiler 10.1
//
//
// Buffer Definitions: 
//
// cbuffer XeTextureTileConstants
// {
//
//   uint xe_texture_tile_guest_base;   // Offset:    0 Size:     4
//   uint xe_texture_tile_info;         // Offset:    4 Size:     4
//   uint xe_texture_tile_offset;       // Offset:    8 Size:     4
//   uint xe_texture_tile_size;         // Offset:   12 Size:     4
//   uint xe_texture_tile_host_base;    // Offset:   16 Size:     4
//   uint xe_texture_tile_host_pitch;   // Offset:   20 Size:     4
//
// }
//
//
// Resource Bindings:
//
// Name                                 Type  Format         Dim      ID      HLSL Bind  Count
// ------------------------------ ---------- ------- ----------- ------- -------------- ------
// xe_texture_tile_source            texture    byte         r/o      T0             t0      1 
// xe_texture_tile_dest                  UAV    byte         r/w      U0             u0      1 
// XeTextureTileConstants            cbuffer      NA          NA     CB0            cb0      1 
//
//
//
// Input signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Input
//
// Output signature:
//
// Name                 Index   Mask Register SysValue  Format   Used
// -------------------- ----- ------ -------- -------- ------- ------
// no Output
cs_5_1
dcl_globalFlags refactoringAllowed
dcl_constantbuffer CB0[0:0][2], immediateIndexed, space=0
dcl_resource_raw T0[0:0], space=0
dcl_uav_raw U0[0:0], space=0
dcl_input vThreadID.xy
dcl_temps 11
dcl_thread_group 8, 32, 1
ushr r0.y, CB0[0][0].w, l(16)
mov r0.x, CB0[0][0].w
and r0.xy, r0.xyxx, l(0x0000ffff, 0x0000ffff, 0, 0)
ubfe r0.z, l(1), l(9), CB0[0][0].y
ishl r0.xy, r0.xyxx, r0.zzzz
ishl r1.x, vThreadID.x, l(2)
mov r1.y, vThreadID.y
uge r0.yw, r1.xxxy, r0.xxxy
or r0.y, r0.w, r0.y
if_nz r0.y
  ret 
endif 
imad r0.y, vThreadID.y, CB0[0][1].y, CB0[0][1].x
ishl r0.w, r1.x, l(2)
iadd r0.y, r0.w, r0.y
ld_raw r2.xyzw, r0.y, T0[0].xyzw
and r0.yw, CB0[0][0].yyyy, l(0, 7, 0, 2)
ubfe r1.z, l(2), l(1), CB0[0][0].y
xor r0.y, r0.y, r1.z
and r0.y, r0.y, l(1)
if_nz r0.y
  ishl r3.xyzw, r2.xyzw, l(8, 8, 8, 8)
  and r3.xyzw, r3.xyzw, l(0xff00ff00, 0xff00ff00, 0xff00ff00, 0xff00ff00)
  ushr r4.xyzw, r2.xyzw, l(8, 8, 8, 8)
  and r4.xyzw, r4.xyzw, l(0x00ff00ff, 0x00ff00ff, 0x00ff00ff, 0x00ff00ff)
  iadd r2.xyzw, r3.xyzw, r4.xyzw
endif 
if_nz r0.w
  ushr r3.xyzw, r2.xyzw, l(16, 16, 16, 16)
  bfi r2.xyzw, l(16, 16, 16, 16), l(16, 16, 16, 16), r2.xyzw, r3.xyzw
endif 
ushr r3.xyzw, CB0[0][0].zzyy, l(5, 10, 10, 19)
mov r4.x, CB0[0][0].z
mov r4.y, r3.x
and r0.yw, r4.xxxy, l(0, 31, 0, 31)
ushr r1.xy, r1.xyxx, r0.zzzz
iadd r0.yw, r0.yyyw, r1.xxxy
bfi r1.xy, l(9, 9, 0, 0), l(5, 5, 0, 0), r3.wzww, l(0, 0, 0, 0)
if_nz r1.x
  iadd r4.xyzw, r0.yyyy, l(0, 1, 2, 3)
  ushr r1.zw, r0.wwww, l(0, 0, 4, 3)
  ubfe r3.x, l(1), l(12), CB0[0][0].z
  ushr r3.zw, r1.xxxy, l(0, 0, 4, 5)
  imad r1.x, r3.x, r3.z, r1.z
  ushr r5.xyzw, r4.xyzw, l(5, 5, 5, 5)
  imad r5.xyzw, r1.xxxx, r3.wwww, r5.xyzw
  ishl r1.x, r0.w, l(10)
  and r1.x, r1.x, l(6144)
  bfi r6.xyzw, l(3, 3, 3, 3), l(8, 8, 8, 8), r4.xyzw, r1.xxxx
  ushr r6.xyzw, r6.xyzw, l(6, 6, 6, 6)
  iadd r1.x, r1.w, r3.x
  ushr r4.xyzw, r4.xyzw, l(3, 3, 3, 3)
  bfi r1.z, l(1), l(1), r1.x, l(0)
  iadd r4.xyzw, r1.zzzz, r4.xyzw
  bfi r4.xyzw, l(2, 2, 2, 2), l(1, 1, 1, 1), r4.xyzw, l(0, 0, 0, 0)
  bfi r4.xyzw, l(1, 1, 1, 1), l(0, 0, 0, 0), r1.xxxx, r4.xyzw
  and r7.xyzw, r6.xyzw, l(112, 112, 112, 112)
  bfi r8.xyzw, l(20, 20, 20, 20), l(10, 10, 10, 10), r5.xyzw, l(0, 0, 0, 0)
  imad r8.xyzw, r7.xyzw, l(2, 2, 2, 2), r8.xyzw
  bfi r8.xyzw, l(4, 4, 4, 4), l(0, 0, 0, 0), r6.xyzw, r8.xyzw
  bfi r8.xyzw, l(2, 2, 2, 2), l(8, 8, 8, 8), r3.yyyy, r8.xyzw
  bfi r9.xyzw, l(1, 1, 1, 1), l(4, 4, 4, 4), r0.wwww, r8.xyzw
  ubfe r8.xyzw, l(3, 3, 3, 3), l(6, 6, 6, 6), r8.xyzw
  and r10.xyzw, r4.xyzw, l(6, 6, 6, 6)
  bfi r4.xyzw, l(1, 1, 1, 1), l(8, 8, 8, 8), r4.xyzw, l(0, 0, 0, 0)
  imad r4.xyzw, r8.xyzw, l(32, 32, 32, 32), r4.xyzw
  imad r4.xyzw, r10.xyzw, l(4, 4, 4, 4), r4.xyzw
  bfi r5.xyzw, l(20, 20, 20, 20), l(13, 13, 13, 13), r5.xyzw, l(0, 0, 0, 0)
  imad r5.xyzw, r7.xyzw, l(16, 16, 16, 16), r5.xyzw
  bfi r5.xyzw, l(4, 4, 4, 4), l(3, 3, 3, 3), r6.xyzw, r5.xyzw
  bfi r3.xyzw, l(2, 2, 2, 2), l(11, 11, 11, 11), r3.yyyy, r5.xyzw
  bfi r3.xyzw, l(1, 1, 1, 1), l(7, 7, 7, 7), r0.wwww, r3.xyzw
  bfi r3.xyzw, l(9, 9, 9, 9), l(3, 3, 3, 3), r4.xyzw, r3.xyzw
  bfi r3.xyzw, l(6, 6, 6, 6), l(0, 0, 0, 0), r9.xyzw, r3.xyzw
else 
  iadd r4.xyzw, r0.yyyy, l(0, 1, 2, 3)
  ushr r5.xyzw, r4.xyzw, l(5, 5, 5, 5)
  ushr r1.xz, r0.wwww, l(5, 0, 2, 0)
  ushr r0.y, r1.y, l(5)
  imad r5.xyzw, r1.xxxx, r0.yyyy, r5.xyzw
  ishl r1.xy, r0.wwww, l(4, 7, 0, 0)
  and r1.xy, r1.xyxx, l(224, 2048, 0, 0)
  bfi r6.xyzw, l(3, 3, 3, 3), l(2, 2, 2, 2), r4.xyzw, r1.xxxx
  ishl r0.y, r1.x, l(1)
  bfi r7.xyzw, l(3, 3, 3, 3), l(3, 3, 3, 3), r4.xyzw, r0.yyyy
  and r7.xyzw, r7.xyzw, l(480, 480, 480, 480)
  bfi r8.xyzw, l(23, 23, 23, 23), l(9, 9, 9, 9), r5.xyzw, r7.xyzw
  bfi r8.xyzw, l(4, 4, 4, 4), l(0, 0, 0, 0), r6.xyzw, r8.xyzw
  bfi r8.xyzw, l(1, 1, 1, 1), l(4, 4, 4, 4), r0.wwww, r8.xyzw
  ishl r9.xyzw, r7.xyzw, l(3, 3, 3, 3)
  bfi r9.xyzw, l(23, 23, 23, 23), l(12, 12, 12, 12), r5.xyzw, r9.xyzw
  bfi r9.xyzw, l(4, 4, 4, 4), l(3, 3, 3, 3), r6.xyzw, r9.xyzw
  bfi r9.xyzw, l(1, 1, 1, 1), l(7, 7, 7, 7), r0.wwww, r9.xyzw
  bfi r9.xyzw, l(12, 12, 12, 12), l(0, 0, 0, 0), r1.yyyy, r9.xyzw
  ishl r7.xyzw, r7.xyzw, l(2, 2, 2, 2)
  bfi r5.xyzw, l(23, 23, 23, 23), l(11, 11, 11, 11), r5.xyzw, r7.xyzw
  bfi r5.xyzw, l(4, 4, 4, 4), l(2, 2, 2, 2), r6.xyzw, r5.xyzw
  bfi r5.xyzw, l(1, 1, 1, 1), l(6, 6, 6, 6), r0.wwww, r5.xyzw
  and r5.xyzw, r5.xyzw, l(1792, 1792, 1792, 1792)
  iadd r5.xyzw, r9.xyzw, r5.xyzw
  ushr r4.xyzw, r4.xyzw, l(3, 3, 3, 3)
  and r0.y, r1.z, l(2)
  iadd r1.xyzw, r0.yyyy, r4.xyzw
  bfi r1.xyzw, l(2, 2, 2, 2), l(6, 6, 6, 6), r1.xyzw, l(0, 0, 0, 0)
  iadd r1.xyzw, r5.xyzw, r1.xyzw
  bfi r3.xyzw, l(6, 6, 6, 6), l(0, 0, 0, 0), r8.xyzw, r1.xyzw
endif 
iadd r1.xyzw, r3.xyzw, CB0[0][0].xxxx
ishl r0.y, r0.z, l(1)
ishl r1.xyzw, r1.xyzw, r0.yyyy
and r0.y, r0.z, vThreadID.y
ishl r0.y, r0.y, l(3)
iadd r1.xyzw, r0.yyyy, r1.xyzw
if_nz r0.z
  iadd r1.xyzw, r1.xxyy, l(0, 4, 0, 4)
endif 
store_raw U0[0].x, r1.x, r2.x
imad r0.yzw, vThreadID.xxxx, l(0, 4, 4, 4), l(0, 1, 2, 3)
ult r0.xyz, r0.yzwy, r0.xxxx
if_nz r0.x
  store_raw U0[0].x, r1.y, r2.y
  if_nz r0.y
    store_raw U0[0].x, r1.z, r2.z
    if_nz r0.z
      store_raw U0[0].x, r1.w, r2.w
    endif 
  endif 
endif 
ret 
// Approximately 129 instruction slots used
