Bibo Mao 15eedfd2ff target/loongarch: Use actual operand size with vbsrl check ... Hardcoded 32 bytes is used for vbsrl emulation check, there is problem when options lsx=on,lasx=off is used for vbsrl.v instruction in TCG mode. It injects LASX exception rather LSX exception. Here actual operand size is used. Cc: qemu-stable@nongnu.org Fixes: df97f33807 ("target/loongarch: Implement xvreplve xvinsve0 xvpickve") Signed-off-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Richard Henderson <richard.henderson@linaro.org> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> (cherry picked from commit d41989e7548397b469ec9c7be4cee699321a317e) Signed-off-by: Michael Tokarev <mjt@tls.msk.ru>		2024-12-29 01:50:54 +03:00
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insn_trans	target/loongarch: Use actual operand size with vbsrl check	2024-12-29 01:50:54 +03:00
constant_timer.c	target/loongarch: move translate modules to tcg/	2024-01-06 10:18:52 +08:00
csr_helper.c	system/cpus: rename qemu_mutex_lock_iothread() to bql_lock()	2024-01-08 10:45:43 -05:00
fpu_helper.c	target/loongarch: Explicitly set 2-NaN propagation rule	2024-11-05 10:09:54 +00:00
iocsr_helper.c	hw/loongarch/virt: Set iocsr address space per-board rather than percpu	2024-01-11 19:22:47 +08:00
meson.build	target/loongarch: move translate modules to tcg/	2024-01-06 10:18:52 +08:00
op_helper.c	mark <zlib.h> with for-crc32 in a consistent manner	2024-09-20 08:06:56 +03:00
tlb_helper.c	target/loongarch: Fix helper_lddir() a CID INTEGER_OVERFLOW issue	2024-07-24 16:52:18 +08:00
translate.c	accel/tcg: Provide default implementation of disas_log	2024-05-15 08:55:18 +02:00
vec_helper.c	target/loongarch: move translate modules to tcg/	2024-01-06 10:18:52 +08:00