xemu/target-arm
Peter Maydell 8387da8197 target-arm: Handle VMOV between two core and VFP single regs
Fix two bugs in the translation of the instructions VMOV sa,sb,rx,ry and
VMOV rx,ry,sa,sb (which copy between a pair of ARM core registers and a
pair of VFP single precision registers):

 * An incorrect condition meant these instruction patterns were being
   treated as load/store multiple, which resulted in the generation
   of bad code and a runtime segfault
 * The order of the core register pair was reversed so the values would
   go to the wrong registers

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
2011-03-06 20:28:08 +01:00
..
cpu.h arm: drop unused irq-related part of CPUARMState 2011-02-11 01:10:13 +01:00
exec.h move cpu_pc_from_tb to target-*/exec.h 2010-07-03 09:48:12 +03:00
helper.c target-arm: fix support for VRSQRTE. 2011-02-24 08:53:36 +01:00
helpers.h target-arm: Move Neon VZIP to helper functions 2011-02-20 17:31:53 +01:00
iwmmxt_helper.c Update to a hopefully more future proof FSF address 2009-07-16 20:47:01 +00:00
machine.c Save/restore ARMv6 MMU state 2009-07-31 13:19:39 +01:00
neon_helper.c target-arm: Fix unsigned VQRSHL by large shift counts 2011-02-20 17:43:01 +01:00
op_addsub.h target-arm: fix addsub/subadd implementation 2010-07-01 23:45:29 +02:00
op_helper.c Set the right overflow bit for neon 32 and 64 bit saturating add/sub. 2011-02-04 20:57:41 +01:00
translate.c target-arm: Handle VMOV between two core and VFP single regs 2011-03-06 20:28:08 +01:00