xemu/target
Weiwei Li eacaf44019 target/riscv: Fix priority of csr related check in riscv_csrrw_check
Normally, riscv_csrrw_check is called when executing Zicsr instructions.
And we can only do access control for existed CSRs. So the priority of
CSR related check, from highest to lowest, should be as follows:
1) check whether Zicsr is supported: raise RISCV_EXCP_ILLEGAL_INST if not
2) check whether csr is existed: raise RISCV_EXCP_ILLEGAL_INST if not
3) do access control: raise RISCV_EXCP_ILLEGAL_INST or RISCV_EXCP_VIRT_
INSTRUCTION_FAULT if not allowed

The predicates contain parts of function of both 2) and 3), So they need
to be placed in the middle of riscv_csrrw_check

Signed-off-by: Weiwei Li <liweiwei@iscas.ac.cn>
Signed-off-by: Junqiang Wang <wangjunqiang@iscas.ac.cn>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Message-Id: <20220803123652.3700-1-liweiwei@iscas.ac.cn>
Signed-off-by: Alistair Francis <alistair.francis@wdc.com>
2022-09-07 09:18:33 +02:00
..
alpha accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
arm accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
avr accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
cris accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
hexagon accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
hppa accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
i386 target/i386: Make translator stop before the end of a page 2022-09-06 08:04:26 +01:00
loongarch accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
m68k accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
microblaze accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
mips accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
nios2 accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
openrisc accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
ppc accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
riscv target/riscv: Fix priority of csr related check in riscv_csrrw_check 2022-09-07 09:18:33 +02:00
rx accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
s390x target/s390x: Make translator stop before the end of a page 2022-09-06 08:04:26 +01:00
sh4 accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
sparc accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
tricore accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
xtensa accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00