xemu/target
Peter Maydell b8f7959f28 target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init
Where architecturally one ARM_FEATURE_X flag implies another
ARM_FEATURE_Y, we allow the CPU init function to only set X, and then
set Y for it.  Currently we do this in two places -- we set a few
flags in arm_cpu_post_init() because we need them to decide which
properties to create on the CPU object, and then we do the rest in
arm_cpu_realizefn().  However, this is fragile, because it's easy to
add a new property and not notice that this means that an X-implies-Y
check now has to move from realize to post-init.

As a specific example, the pmsav7-dregion property is conditional
on ARM_FEATURE_PMSA && ARM_FEATURE_V7, which means it won't appear
on the Cortex-M33 and -M55, because they set ARM_FEATURE_V8 and
rely on V8-implies-V7, which doesn't happen until the realizefn.

Move all of these X-implies-Y checks into a new function, which
we call at the top of arm_cpu_post_init(), so the feature bits
are available at that point.

This does now give us the reverse issue, that if there's a feature
bit which is enabled or disabled by the setting of a property then
then X-implies-Y features that are dependent on that property need to
be in realize, not in this new function.  But the only one of those
is the "EL3 implies VBAR" which is already in the right place, so
putting things this way round seems better to me.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-id: 20230724174335.2150499-2-peter.maydell@linaro.org
2023-08-31 11:05:04 +01:00
..
alpha target/alpha: Use tcg_gen_movcond_i64 in gen_fold_mzero 2023-08-24 11:22:42 -07:00
arm target/arm: Do all "ARM_FEATURE_X implies Y" checks in post_init 2023-08-31 11:05:04 +01:00
avr target/avr: Fix handling of interrupts above 33. 2023-07-08 07:24:38 +03:00
cris target/cris: Fix a typo in gen_swapr() 2023-08-24 11:22:42 -07:00
hexagon target: Widen pc/cs_base in cpu_get_tb_cpu_state 2023-06-26 17:32:59 +02:00
hppa target/hppa: Switch to use MMU indices 11-15 2023-08-27 17:15:19 +02:00
i386 accel/*: Widen pc/saved_insn for *_sw_breakpoint 2023-08-28 16:07:04 -04:00
loongarch target/loongarch: Split fcc register to fcc0-7 in gdbstub 2023-08-24 11:17:59 +08:00
m68k target/m68k: Use tcg_gen_negsetcond_* 2023-08-24 11:22:42 -07:00
microblaze other architectures: spelling fixes 2023-07-25 17:14:07 +03:00
mips mips: Report an error when KVM_VM_MIPS_VZ is unavailable 2023-08-22 17:31:03 +01:00
nios2 target/nios2: Fix semihost lseek offset computation 2023-08-01 23:52:23 +02:00
openrisc target/openrisc: Use tcg_gen_negsetcond_* 2023-08-24 11:22:42 -07:00
ppc target/ppc: Use tcg_gen_negsetcond_* 2023-08-24 11:22:42 -07:00
riscv include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*() 2023-08-24 11:21:46 -07:00
rx include/exec: Replace target_ulong with abi_ptr in cpu_[st|ld]*() 2023-08-24 11:21:46 -07:00
s390x sysemu/kvm: Use vaddr for kvm_arch_[insert|remove]_hw_breakpoint 2023-08-24 11:21:35 -07:00
sh4 target: Widen pc/cs_base in cpu_get_tb_cpu_state 2023-06-26 17:32:59 +02:00
sparc target/sparc: Use tcg_gen_movcond_i64 in gen_edge 2023-08-24 11:22:42 -07:00
tricore target/tricore: Replace gen_cond_w with tcg_gen_negsetcond_tl 2023-08-24 11:22:42 -07:00
xtensa target/xtensa: Assert that interrupt level is within bounds 2023-07-06 13:26:43 +01:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00