xemu/target
Peter Maydell dde4d028dc target/arm: Make cpregs 0, c0, c{3-15}, {0-7} correctly RAZ in v8
In the AArch32 ID register scheme, coprocessor registers with
encoding cp15, 0, c0, c{0-7}, {0-7} are all in the space covered by
what in v6 and v7 was called the "CPUID scheme", and are supposed to
RAZ if they're not allocated to a specific ID register.  For our
pre-v8 CPUs we get this right, because the regdefs in
id_pre_v8_midr_cp_reginfo[] cover these RAZ requirements.  However
for v8 we failed to put in the necessary patterns to cover this, so
we end up UNDEFing on everything we didn't have an ID register for.
This is a problem because in Armv8 some encodings in 0, c0, c3, {0-7}
are now being used for new ID registers, and guests might thus start
trying to read them.  (We already have one of these: ID_PFR2.)

For v8 CPUs, we already have regdefs for 0, c0, c{0-2}, {0-7} (that
is, the space is completely allocated with no reserved spaces).  Add
entries to v8_idregs[] covering 0, c0, c3, {0-7}:
 * c3, {0-2} is the reserved AArch32 space corresponding to the
   AArch64 MVFR[012]_EL1
 * c3, {3,5,6,7} are reserved RAZ for both AArch32 and AArch64
   (in fact some of these are given defined meanings in Armv8.6,
   but we don't implement them yet)
 * c3, 4 is ID_PFR2 (already defined)

We then programmatically add RAZ patterns for AArch32 for
0, c0, c{4..15}, {0-7}:
 * c4-c7 are unused, and not shared with AArch64 (these
   are the encodings corresponding to where the AArch64
   specific ID registers live in the system register space)
 * c8-c15 weren't required to RAZ in v6/v7, but v8 extends
   the AArch32 reserved-should-RAZ space to cover these;
   the equivalent area of the AArch64 sysreg space is not
   defined as must-RAZ

Note that the architecture allows some registers in this space
to return an UNKNOWN value; we always return 0.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Message-Id: <20220819110052.2942289-2-peter.maydell@linaro.org>
Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
2022-09-14 11:19:39 +01:00
..
alpha accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
arm target/arm: Make cpregs 0, c0, c{3-15}, {0-7} correctly RAZ in v8 2022-09-14 11:19:39 +01:00
avr accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
cris accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
hexagon accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
hppa accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
i386 target/i386: Make translator stop before the end of a page 2022-09-06 08:04:26 +01:00
loongarch accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
m68k accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
microblaze accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
mips accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
nios2 accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
openrisc accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
ppc accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
riscv target/riscv: Update the privilege field for sscofpmf CSRs 2022-09-07 09:19:15 +02:00
rx accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
s390x target/s390x: Make translator stop before the end of a page 2022-09-06 08:04:26 +01:00
sh4 accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
sparc accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
tricore accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
xtensa accel/tcg: Add pc and host_pc params to gen_intermediate_code 2022-09-06 08:04:26 +01:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00