xemu/target/ppc/translate
Paul A. Clarke 256be7d07a ppc: Fix xsmaddmdp and friends
A class of instructions of the form:
  op Target,A,B
which operate like:
  Target = Target * A + B
have a bit set which distinguishes them from instructions that operate as:
  Target = Target * B + A

This bit is not being checked properly (using PPC_BIT macro), so all
instructions in this class are operating incorrectly as the second form
above.  The bit was being checked as if it were part of a 64-bit
instruction opcode, rather than a proper 32-bit opcode.  Fix by using the
macro (PPC_BIT32) which treats the opcode as a 32-bit quantity.

Fixes: c9f4e4d8b6 ("target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro")

Signed-off-by: Paul A. Clarke <pc@us.ibm.com>
Message-Id: <1566401321-22419-1-git-send-email-pc@us.ibm.com>
Reviewed-by: Laurent Vivier <lvivier@redhat.com>
Tested-by: Laurent Vivier <lvivier@redhat.com>
Signed-off-by: David Gibson <david@gibson.dropbear.id.au>
2019-08-29 09:46:07 +10:00
..
dfp-impl.inc.c target/ppc: move FP and VMX registers into aligned vsr register array 2019-01-09 09:28:14 +11:00
dfp-ops.inc.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
fp-impl.inc.c ppc: Add support for 'mffsl' instruction 2019-08-21 17:17:39 +10:00
fp-ops.inc.c ppc: Add support for 'mffsl' instruction 2019-08-21 17:17:39 +10:00
spe-impl.inc.c target/ppc: Use tcg_gen_abs_i32 2019-05-13 22:52:08 +00:00
spe-ops.inc.c Move target-* CPU file into a target/ folder 2016-12-20 21:52:12 +01:00
vmx-impl.inc.c target/ppc: Optimize emulation of vclzw instruction 2019-08-21 17:17:11 +10:00
vmx-ops.inc.c Changes requirement for "vsubsbs" instruction 2018-12-21 09:29:12 +11:00
vsx-impl.inc.c ppc: Fix xsmaddmdp and friends 2019-08-29 09:46:07 +10:00
vsx-ops.inc.c target/ppc: improve VSX_FMADD with new GEN_VSX_HELPER_VSX_MADD macro 2019-07-02 09:43:58 +10:00