xemu/target
Peter Maydell ca4d5d862d target/sparc: Handle FPRS correctly on big-endian hosts
In CPUSparcState we define the fprs field as uint64_t.  However we
then refer to it in translate.c via a TCGv_i32 which we set up with
tcg_global_mem_new_ptr().  This means that on a big-endian host when
the guest does something to writo te the FPRS register this value
ends up in the wrong half of the uint64_t, and the QEMU C code that
refers to env->fprs sees the wrong value.  The effect of this is that
guest code that enables the FPU crashes with spurious FPU Disabled
exceptions.  In particular, this is why
 tests/avocado/machine_sparc64_sun4u.py:Sun4uMachine.test_sparc64_sun4u
times out on an s390 host.

There are multiple ways we could fix this; since there are actually
only three bits in the FPRS register and the code in translate.c
would be a bit painful to convert to dealing with a TCGv_i64, change
the type of the CPU state struct field to match what translate.c is
expecting.

(None of the other fields referenced by the r32[] array in
sparc_tcg_init() have the wrong type.)

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
Reviewed-by: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>
Message-Id: <20230717103544.637453-1-peter.maydell@linaro.org>
2023-07-25 14:42:00 +02:00
..
alpha target/alpha: Use float64_to_int64_modulo for CVTTQ 2023-07-01 08:26:54 +02:00
arm target/arm/ptw.c: Account for FEAT_RME when applying {N}SW, SA bits 2023-07-17 11:05:08 +01:00
avr target/avr: Fix handling of interrupts above 33. 2023-07-08 07:24:38 +03:00
cris target: Widen pc/cs_base in cpu_get_tb_cpu_state 2023-06-26 17:32:59 +02:00
hexagon target: Widen pc/cs_base in cpu_get_tb_cpu_state 2023-06-26 17:32:59 +02:00
hppa accel/tcg: Return bool from page_check_range 2023-07-15 08:02:32 +01:00
i386 target/i386: Use aesdec_ISB_ISR_IMC_AK 2023-07-08 07:30:18 +01:00
loongarch target/loongarch: Fix the CSRRD CPUID instruction on big endian hosts 2023-07-24 18:44:48 +02:00
m68k target: Widen pc/cs_base in cpu_get_tb_cpu_state 2023-06-26 17:32:59 +02:00
microblaze target/microblaze: Define TCG_GUEST_DEFAULT_MO 2023-06-26 17:33:00 +02:00
mips target/mips: Avoid shift by negative number in page_table_walk_refill() 2023-07-25 14:41:16 +02:00
nios2 target/nios2 : Explicitly ask for target-endian loads and stores 2023-07-01 08:26:54 +02:00
openrisc target: Widen pc/cs_base in cpu_get_tb_cpu_state 2023-06-26 17:32:59 +02:00
ppc target/ppc: Use aesdec_ISB_ISR_AK_IMC 2023-07-08 07:30:17 +01:00
riscv target/riscv: Fix LMUL check to use VLEN 2023-07-19 14:37:26 +10:00
rx target: Widen pc/cs_base in cpu_get_tb_cpu_state 2023-06-26 17:32:59 +02:00
s390x target/s390x: Fix assertion failure in VFMIN/VFMAX with type 13 2023-07-24 18:44:47 +02:00
sh4 target: Widen pc/cs_base in cpu_get_tb_cpu_state 2023-06-26 17:32:59 +02:00
sparc target/sparc: Handle FPRS correctly on big-endian hosts 2023-07-25 14:42:00 +02:00
tricore target: Widen pc/cs_base in cpu_get_tb_cpu_state 2023-06-26 17:32:59 +02:00
xtensa target/xtensa: Assert that interrupt level is within bounds 2023-07-06 13:26:43 +01:00
Kconfig hw/loongarch: Add support loongson3 virt machine type. 2022-06-06 18:09:03 +00:00
meson.build target/loongarch: Add target build suport 2022-06-06 18:09:03 +00:00